Qsys clock crossing adapter option under project settings, what is the purpose of it?

[Altera_Forum]

I know of clock cross bridge that we may want to use in Qsys. I think we shall have to use it if we have 2 clock sources within our Qsys design which I think is quite possible right? 

 I was wondering what does the Qsys clock crossing adapter option mean, what does it do? We only have 1 clock in the design so what is the purpose of this option? We can use clock crossing bridges anyway if the need exists.

[Altera_Forum]

The option is described here: 

http://www.altera.com/literature/hb/qts/qsys_intro.pdf on page 7-14.  Qsys does not force you to add Clock Crossing Bridge components to your design. You can connect a master from one clock domain to a slave in another clock domain, and Qsys will automatically generate some code for you. This option affects the style of that automatically generated code.  My suggestion would be to always add Clock Crossing Bridges yourself and do not rely on Qsys to automatically generate the clock crossing code for you. It will of course work correctly, but it will consume unnecessary resources as each master/slave connection is handled independently.  You really should try to have a system topology similar to Figure 10-24 on page 10-35 of this document: http://www.altera.com/literature/hb/qts/qsys_optimize.pdf

[Altera_Forum]

Thanks, thats all.