Qsys memory address overlap

[Altera_Forum]

I wrote custum cpu module for Renesas SH4A interface and conect it to 

Qsys (V12.0) via standard Avalon MM master interface. Basic operations are working fine (such as memory test, memory dump, DMA) except DDR2 memory address overlap problem. This probrem is mentioned in ALTERA Wiki.   Qsys Interconnect and Avalon Interface Issues Native Addressing Issue: Qsys does not support native addressing. Qsys will treat all natively address Avalon-MM slave interfaces as dynamically addressed 32-bit interfaces. Workaround: Update any of your own natively addressed custom components to use dynamic addressing and include byte enables for the interface. Merlin Address Routers for Custom peripherals.   There is a sample workaround for Nios cpu. But I can not find the way to use dynamic addressing for my custom cpu module. Please help me to write dynamic addressing Avalon master.   Addition. To write dynamic addressing Avalon master is not my purpose, but all I like to know is how to avoid address overlap problem.   In case of attached memory map, address 0x2010_0000--0x201f_ffff and 0x0010_0000--0x001f_ffff are overlaped.