Qsys not generating same files in Simulation folder for VHDL vs Verilog?

Altera_Forum · ‎11-20-2016

So I have wondered what is going on here and it seems there is a bug in the program. I am using Altera Quartus II 15.0 64 bit.

I select SRAM/SSRAM controller from the IP catalog. Then I click generate HDL and select Verilog for the "simulation" tab. Now I repeat the same process but select VHDL instead of verilog.

I notice that when I select VHDL I do not get a folder called "submodules" in the simulation folder. However, when I select Verilog, I do. The submodules folder is created and it contains a .v file containing source code for the SRAM/SSRAM controller. Why are different files being generated in the two cases? :confused:

This seems to be a bug in the program. :mad:

Altera_Forum · ‎11-21-2016

It looks like these are maybe components which are only generated in Verilog output. So when you say "VHDL" it is still generating Verilog output for these components. At least when I try, specifying VHDL, Qsys does generate .v file for the controller, same as if Verilog had been requested.

It may not be a bug, it may be deliberate that only Verilog language is supported for generating the file.

Altera_Forum · ‎11-21-2016

(duplicate)

Altera_Forum · ‎11-21-2016

when I select VHDL a folder named submodels is not creating in the folder named simulation which means that I cannot carry out simulation. Atleast it should give me a warning message for this but it does not. For 2 full days I was confused what is going on since I am new to Qsys as well.

Altera_Forum · ‎11-21-2016

This works fine here. If I create an empty Qsys with the SDRAM controller, select language "VHDL" and Generate the system, I am left with foo/simulation/submodules and foo/synthesis/submodules/ directories, both of which have identical copies of the Verilog instance of the controller.

I also have foo/simulation/foo.vhd with the top level.

Are you confusing the "foo/simulation" subdirectory with the top-level "simulation" directory? Qsys puts everything in a new subdirectory of the same name as your Qsys file. The "simulation" folder in your Quartus project directory is for e.g. the gate level / timing accurate simulation models generated as an output of the Quartus compilation.