Hello,
I'm facing a problem with my Qsys generated testbench. I generated a VHDL testbench from Qsys. In Qsys I used three own components and one clock input, all connected using Avalon Streaming Interface. I checked all signals and connections. When I start the testbench in ModelSim, it compiles and then gives a warning that all my components are not bound in the testbench file. Afterwards nothing happens in the simulation as not component is actually simulated. I checked the ModelSim script and the compile order is ok, I also compiled the VHDL files of my components myself in ModelSim and all is fine. What is the reason I get these warnings?
# Loading testbench_inst.testbench(rtl)# ** Warning: (vsim-3473) Component instance "avalon_sink_tb_0 : testbench_Avalon_Sink_TB_0" is not bound.# Time: 0 ps Iteration: 0 Instance: /testbench_tb/testbench_inst File: ./../testbench_tb/simulation/submodules/testbench.vhd# ** Warning: (vsim-3473) Component instance "avalon_sink_tb_1 : testbench_Avalon_Sink_TB_1" is not bound.# Time: 0 ps Iteration: 0 Instance: /testbench_tb/testbench_inst File: ./../testbench_tb/simulation/submodules/testbench.vhd# ** Warning: (vsim-3473) Component instance "avalon_source_tb_0 : testbench_Avalon_Source_TB_0" is not bound.# Time: 0 ps Iteration: 0 Instance: /testbench_tb/testbench_inst File: ./../testbench_tb/simulation/submodules/testbench.vhd# ** Warning: (vsim-3473) Component instance "distribution_pixel_0 : testbench_Distribution_Pixel_0" is not bound.# Time: 0 ps Iteration: 0 Instance: /testbench_tb/testbench_inst File: ./../testbench_tb/simulation/submodules/testbench.vhd
Quartus 15.1 and ModelSim 10.3, target device: CycloneV SOC
