Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Quartus 18.1 doesnot create .sdo files

RVadl2
Novice
2,762 Views

I am using a Cyclone 10 LP FPGA for my project along with Quartus 18.1 for design development. I am able to run the functional simulation but I am not able to generate .sdo files for performing Timing simulation.

Can you help me on this?

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2 Replies
Kenny_Tan
Moderator
2,696 Views

The gate level simulation is not supported in V series of device. You can refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii53025.pdf page 1-2

Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level timing simulation is supported only for the Stratix IV and Cyclone IV device families. Use TimeQuest static timing analysis rather than gate-level timing simulation

Make sure you go to assignement -> Settings -> EDA Tools Simulation -> generate functional simulation netlist -> turn it to on.

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Jeremy_J_
Novice
2,696 Views

Make sure you go to assignement -> Settings -> EDA Tools Simulation -> generate functional simulation netlist -> turn it to on.

 

This is wrong, please turn it off then you got .sdo file generated

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