There is a procedure from TrustHub to implement AES-1800 using XILINX. I believe I can use the design flow in general but need to develop my application with Quartus/Intel-Altera. When I setup the new project wizard and click finish, Quartus 21.1 becomes unresponsive, and I have to end the Quartus task. Can you provide a like procedure for Quartus/Intel-Altera? Please provide technical support.
This sounds like an installation issue. Please reinstall the Quartus software.
If you still see the issue, can you let me know what device you are targeting and which Quartus version you are using? (Pro/Standard/Lite?)
Thanks Nurina. After reinstalling, the problem is unfortunately still there. Targeting the Altera Cyclone V 5CEBA4F23C7N on the Terasic DE0-CV FPGA Board using Quartus Prime Standard Edition, version 21.1
Only these OS are supported. Are you using any of them?
- CentOS(*) 7.7
- CentOS 8.2
- Red Hat(*) Enterprise Linux(*) 7.7
- Red Hat Enterprise Linux 8.2
- SUSE(*) Linux Enterprise Server 12.0 SP5
- SUSE Linux Enterprise Server 15.0 LTS
- Ubuntu(*) 16.04.06
- Ubuntu 18.04.01
- Ubuntu 20.04 LTS
- Windows(*) 10
- Windows Server(*) 2012
- Windows Server 2016
- Windows Server 2019
Are you following the disk space and memory recommendations as stated here? https://www.intel.com/content/www/us/en/docs/programmable/683593/22-1/disk-space-and-memory-recommen...
Was able to resolve various setup and licensing related issues: the design is now running compile with following errors:
Error (12061): Can't synthesize current design -- Top partition does not contain any logic
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 10 warnings
Error: Peak virtual memory: 4824 megabytes
Error: Processing ended: Fri Jan 20 10:52:35 2023
Error: Elapsed time: 00:00:08
Error: Total CPU time (on all processors): 00:00:17
Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 10 warnings
Unfortunately, am still getting errors. Can you help via remote debugging session?
Error (169281): There are 257 IO input pads in the design, but only 224 IO input pad locations available on the device.