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Quartus 21.1 couldn't execute "perl"

T2
Novice
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Quartus: 21.1.0 Build 842

Windows 10 Pro for workstations: 10.0.19044

Additional installs: Ubuntu 18.04 LTS and WSL (0.2.1-1)

 

Upgrading a project from Quartus 13.1.
Platform Design IP upgrades were all successful.
Generation fails when first instance of fifoed_avalon_uart is encountered.  See below for log messages at the point of the error and full log.  

Several years ago encountered this in migration to Quartus 13.1.  Required editing "fifoed_avalon_uart_hw.tcl" to correct path to perl.  Unable to find and fix where link is broken.  Searching forum has not yielded a solution.

 

Log at point of error:

----------------------------------------------------------------------------------

Info: pa_uart: Starting FIFOed UART Generation
Info: pa_uart: exec perl -I . -I C:/intelfpga/21.1/quartus/sopc_builder/bin/ -I C:/intelfpga/21.1/quartus/sopc_builder/bin//europa/ -I C:/intelfpga/21.1/quartus/sopc_builder/bin//perl_lib/ mk_em_uart_sa.pl --_system_directory=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0052_sopcgen/ --language=verilog --name=sopc_pa_uart --clock_freq=93333300 --use_tx_fifo=1 --use_rx_fifo=1 --baud=57600 --data_bits=8 --fixed_baud=0 --parity=N --stop_bits=1 --use_cts_rts=0 --use_eop_register=0 --sim_true_baud=0 --fifo_export_used=0 --Has_IRQ=1 --hw_cts=0 --trans_pin=0 --fifo_size_tx=16 --fifo_size_rx=16 --use_timout=0 --timeout_value=4 --rx_IRQ_Threshold=1 --tx_IRQ_Threshold=1 --tx_fifo_LE=0 --rx_fifo_LE=0 --use_gap_detection=0 --gap_value=4 --use_timestamp=0 --use_ext_timestamp=0 --timestamp_width=8 --add_error_bits=0
Error: pa_uart: couldn't execute "perl": no such file or directory
while executing
"exec perl -I . -I C:/intelfpga/21.1/quartus/sopc_builder/bin/ -I C:/intelfpga/21.1/quartus/sopc_builder/bin//europa/ -I C:/intelfpga/21.1/quartus/sopc..."
("eval" body line 1)
invoked from within
"eval $exec_list"
(procedure "generate" line 70)
invoked from within
"generate"

----------------------------------------------------------------------------------

 

Full log:

----------------------------------------------------------------------------------

Info: Saving generation log to C:/Quasonix/projects/transmitter/DTx_Q21/fpga/common/sopc/sopc/sopc_generation.rpt
Info: Starting: Create simulation model
Info: qsys-generate C:\Quasonix\projects\transmitter\DTx_Q21\fpga\common\sopc\sopc.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=C:\Quasonix\projects\transmitter\DTx_Q21\fpga\common\sopc\sopc\simulation --family="Cyclone V" --part=5CEFA7U19I7
Progress: Loading sopc/sopc.qsys
Progress: Reading input file
Progress: Adding boot_rom [altera_avalon_onchip_memory2 21.1]
Progress: Parameterizing module boot_rom
Progress: Adding clk [clock_source 21.1]
Progress: Parameterizing module clk
Progress: Adding ext_flash_controller [altera_avalon_epcs_flash_controller 21.1]
Progress: Parameterizing module ext_flash_controller
Progress: Adding ext_sram_bridge [altera_tristate_conduit_bridge 21.1]
Progress: Parameterizing module ext_sram_bridge
Progress: Adding ext_sram_controller [altera_generic_tristate_controller 21.1]
Progress: Parameterizing module ext_sram_controller
Progress: Adding fpga_interrupt [altera_avalon_pio 21.1]
Progress: Parameterizing module fpga_interrupt
Progress: Adding fpga_io [altera_merlin_slave_translator 21.1]
Progress: Parameterizing module fpga_io
Progress: Adding int_sram [altera_avalon_onchip_memory2 21.1]
Progress: Parameterizing module int_sram
Progress: Adding jtag_uart [altera_avalon_jtag_uart 21.1]
Progress: Parameterizing module jtag_uart
Progress: Adding nios2 [altera_nios2_gen2 21.1]
Progress: Parameterizing module nios2
Progress: Adding pa_uart [fifoed_avalon_uart 9.3.0]
Progress: Parameterizing module pa_uart
Progress: Adding stamp_timer [altera_avalon_timer 21.1]
Progress: Parameterizing module stamp_timer
Progress: Adding sys_id [altera_avalon_sysid_qsys 21.1]
Progress: Parameterizing module sys_id
Progress: Adding tick_timer [altera_avalon_timer 21.1]
Progress: Parameterizing module tick_timer
Progress: Adding tophat_uart [fifoed_avalon_uart 9.3.0]
Progress: Parameterizing module tophat_uart
Progress: Adding user_uart [fifoed_avalon_uart 9.3.0]
Progress: Parameterizing module user_uart
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: sopc.ext_flash_controller: Legacy EPCS/EPCQx1 Flash Controller will only be supported in Quartus Prime Standard Edition in the future release.
Warning: sopc.ext_sram_controller: Properties (isMemoryDevice) have been set on interface uas - in composed mode these are ignored
Info: sopc.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: sopc.sys_id: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: sopc.sys_id: Time stamp will be automatically updated when this component is generated.
Info: sopc: Generating sopc "sopc" for SIM_VHDL
Warning: sopc: "No matching role found for user_uart:s1:dataavailable (dataavailable)"
Warning: sopc: "No matching role found for user_uart:s1:readyfordata (readyfordata)"
Warning: sopc: "No matching role found for tophat_uart:s1:dataavailable (dataavailable)"
Warning: sopc: "No matching role found for tophat_uart:s1:readyfordata (readyfordata)"
Warning: sopc: "No matching role found for pa_uart:s1:dataavailable (dataavailable)"
Warning: sopc: "No matching role found for pa_uart:s1:readyfordata (readyfordata)"
Info: boot_rom: Starting RTL generation for module 'sopc_boot_rom'
Info: boot_rom: Generation command is [exec C:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/21.1/quartus/bin64/perl/lib -I C:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/21.1/quartus/sopc_builder/bin -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=sopc_boot_rom --dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0036_boot_rom_gen/ --quartus_dir=C:/intelfpga/21.1/quartus --vhdl --config=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0036_boot_rom_gen//sopc_boot_rom_component_configuration.pl --do_build_sim=1 --sim_dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0036_boot_rom_gen/ ]
Info: boot_rom: Done RTL generation for module 'sopc_boot_rom'
Info: boot_rom: "sopc" instantiated altera_avalon_onchip_memory2 "boot_rom"
Info: ext_flash_controller: Starting RTL generation for module 'sopc_ext_flash_controller'
Info: ext_flash_controller: Generation command is [exec C:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/21.1/quartus/bin64/perl/lib -I C:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/21.1/quartus/sopc_builder/bin -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_epcs_flash_controller -- C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_epcs_flash_controller/generate_rtl.pl --name=sopc_ext_flash_controller --dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0037_ext_flash_controller_gen/ --quartus_dir=C:/intelfpga/21.1/quartus --vhdl --config=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0037_ext_flash_controller_gen//sopc_ext_flash_controller_component_configuration.pl --do_build_sim=1 --sim_dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0037_ext_flash_controller_gen/ ]
Info: ext_flash_controller: Done RTL generation for module 'sopc_ext_flash_controller'
Info: ext_flash_controller: "sopc" instantiated altera_avalon_epcs_flash_controller "ext_flash_controller"
Info: ext_sram_bridge: "sopc" instantiated altera_tristate_conduit_bridge "ext_sram_bridge"
Info: ext_sram_controller: "sopc" instantiated altera_generic_tristate_controller "ext_sram_controller"
Info: fpga_interrupt: Starting RTL generation for module 'sopc_fpga_interrupt'
Info: fpga_interrupt: Generation command is [exec C:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/21.1/quartus/bin64/perl/lib -I C:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/21.1/quartus/sopc_builder/bin -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=sopc_fpga_interrupt --dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0039_fpga_interrupt_gen/ --quartus_dir=C:/intelfpga/21.1/quartus --vhdl --config=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0039_fpga_interrupt_gen//sopc_fpga_interrupt_component_configuration.pl --do_build_sim=1 --sim_dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0039_fpga_interrupt_gen/ ]
Info: fpga_interrupt: Done RTL generation for module 'sopc_fpga_interrupt'
Info: fpga_interrupt: "sopc" instantiated altera_avalon_pio "fpga_interrupt"
Info: fpga_io: "sopc" instantiated altera_merlin_slave_translator "fpga_io"
Info: int_sram: Starting RTL generation for module 'sopc_int_sram'
Info: int_sram: Generation command is [exec C:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/21.1/quartus/bin64/perl/lib -I C:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/21.1/quartus/sopc_builder/bin -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=sopc_int_sram --dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0041_int_sram_gen/ --quartus_dir=C:/intelfpga/21.1/quartus --vhdl --config=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0041_int_sram_gen//sopc_int_sram_component_configuration.pl --do_build_sim=1 --sim_dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0041_int_sram_gen/ ]
Info: int_sram: Done RTL generation for module 'sopc_int_sram'
Info: int_sram: "sopc" instantiated altera_avalon_onchip_memory2 "int_sram"
Info: jtag_uart: Starting RTL generation for module 'sopc_jtag_uart'
Info: jtag_uart: Generation command is [exec C:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/21.1/quartus/bin64/perl/lib -I C:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/21.1/quartus/sopc_builder/bin -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=sopc_jtag_uart --dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0042_jtag_uart_gen/ --quartus_dir=C:/intelfpga/21.1/quartus --vhdl --config=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0042_jtag_uart_gen//sopc_jtag_uart_component_configuration.pl --do_build_sim=1 --sim_dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0042_jtag_uart_gen/ ]
Info: jtag_uart: Done RTL generation for module 'sopc_jtag_uart'
Info: jtag_uart: "sopc" instantiated altera_avalon_jtag_uart "jtag_uart"
Info: nios2: "sopc" instantiated altera_nios2_gen2 "nios2"
Info: pa_uart: Starting FIFOed UART Generation
Info: pa_uart: exec perl -I . -I C:/intelfpga/21.1/quartus/sopc_builder/bin/ -I C:/intelfpga/21.1/quartus/sopc_builder/bin//europa/ -I C:/intelfpga/21.1/quartus/sopc_builder/bin//perl_lib/ mk_em_uart_sa.pl --_system_directory=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0043_sopcgen/ --language=vhdl --name=sopc_pa_uart --clock_freq=93333300 --use_tx_fifo=1 --use_rx_fifo=1 --baud=57600 --data_bits=8 --fixed_baud=0 --parity=N --stop_bits=1 --use_cts_rts=0 --use_eop_register=0 --sim_true_baud=0 --fifo_export_used=0 --Has_IRQ=1 --hw_cts=0 --trans_pin=0 --fifo_size_tx=16 --fifo_size_rx=16 --use_timout=0 --timeout_value=4 --rx_IRQ_Threshold=1 --tx_IRQ_Threshold=1 --tx_fifo_LE=0 --rx_fifo_LE=0 --use_gap_detection=0 --gap_value=4 --use_timestamp=0 --use_ext_timestamp=0 --timestamp_width=8 --add_error_bits=0
Error: pa_uart: couldn't execute "perl": no such file or directory
while executing
"exec perl -I . -I C:/intelfpga/21.1/quartus/sopc_builder/bin/ -I C:/intelfpga/21.1/quartus/sopc_builder/bin//europa/ -I C:/intelfpga/21.1/quartus/sopc..."
("eval" body line 1)
invoked from within
"eval $exec_list"
(procedure "generate" line 70)
invoked from within
"generate"
Error: pa_uart: Generation callback did not provide a top level file (expected `add_file $output_dir/sopc_pa_uart.v|vhd|sv {SIMULATION SYNTHESIS}`)
Warning: pa_uart: No files generated for fileset SIM_VHDL
Info: pa_uart: "sopc" instantiated fifoed_avalon_uart "pa_uart"
Error: Generation stopped, 12 or more modules remaining
Info: sopc: Done "sopc" with 21 modules, 12 files
Error: qsys-generate failed with exit code 1: 3 Errors, 8 Warnings
Info: Finished: Create simulation model
Info: Starting: Create Modelsim Project.
Info: sim-script-gen --spd=C:\Quasonix\projects\transmitter\DTx_Q21\fpga\common\sopc\sopc\sopc.spd --output-directory=C:/Quasonix/projects/transmitter/DTx_Q21/fpga/common/sopc/sopc/simulation/ --use-relative-paths=true
Info: Doing: ip-make-simscript --spd=C:\Quasonix\projects\transmitter\DTx_Q21\fpga\common\sopc\sopc\sopc.spd --output-directory=C:/Quasonix/projects/transmitter/DTx_Q21/fpga/common/sopc/sopc/simulation/ --use-relative-paths=true
Info: Generating the following file(s) for MODELSIM simulator in C:/Quasonix/projects/transmitter/DTx_Q21/fpga/common/sopc/sopc/simulation/ directory:
Info: mentor/msim_setup.tcl
Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
Info: Generating the following file(s) for VCSMX simulator in C:/Quasonix/projects/transmitter/DTx_Q21/fpga/common/sopc/sopc/simulation/ directory:
Info: synopsys/vcsmx/synopsys_sim.setup
Info: synopsys/vcsmx/vcsmx_setup.sh
Info: Generating the following file(s) for NCSIM simulator in C:/Quasonix/projects/transmitter/DTx_Q21/fpga/common/sopc/sopc/simulation/ directory:
Info: cadence/cds.lib
Info: cadence/hdl.var
Info: cadence/ncsim_setup.sh
Info: 9 .cds.lib files in cadence/cds_libs/ directory
Info: Generating the following file(s) for RIVIERA simulator in C:/Quasonix/projects/transmitter/DTx_Q21/fpga/common/sopc/sopc/simulation/ directory:
Info: aldec/rivierapro_setup.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/Quasonix/projects/transmitter/DTx_Q21/fpga/common/sopc/sopc/simulation/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create Modelsim Project.
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\Quasonix\projects\transmitter\DTx_Q21\fpga\common\sopc\sopc.qsys --block-symbol-file --output-directory=C:\Quasonix\projects\transmitter\DTx_Q21\fpga\common\sopc\sopc --family="Cyclone V" --part=5CEFA7U19I7
Progress: Loading sopc/sopc.qsys
Progress: Reading input file
Progress: Adding boot_rom [altera_avalon_onchip_memory2 21.1]
Progress: Parameterizing module boot_rom
Progress: Adding clk [clock_source 21.1]
Progress: Parameterizing module clk
Progress: Adding ext_flash_controller [altera_avalon_epcs_flash_controller 21.1]
Progress: Parameterizing module ext_flash_controller
Progress: Adding ext_sram_bridge [altera_tristate_conduit_bridge 21.1]
Progress: Parameterizing module ext_sram_bridge
Progress: Adding ext_sram_controller [altera_generic_tristate_controller 21.1]
Progress: Parameterizing module ext_sram_controller
Progress: Adding fpga_interrupt [altera_avalon_pio 21.1]
Progress: Parameterizing module fpga_interrupt
Progress: Adding fpga_io [altera_merlin_slave_translator 21.1]
Progress: Parameterizing module fpga_io
Progress: Adding int_sram [altera_avalon_onchip_memory2 21.1]
Progress: Parameterizing module int_sram
Progress: Adding jtag_uart [altera_avalon_jtag_uart 21.1]
Progress: Parameterizing module jtag_uart
Progress: Adding nios2 [altera_nios2_gen2 21.1]
Progress: Parameterizing module nios2
Progress: Adding pa_uart [fifoed_avalon_uart 9.3.0]
Progress: Parameterizing module pa_uart
Progress: Adding stamp_timer [altera_avalon_timer 21.1]
Progress: Parameterizing module stamp_timer
Progress: Adding sys_id [altera_avalon_sysid_qsys 21.1]
Progress: Parameterizing module sys_id
Progress: Adding tick_timer [altera_avalon_timer 21.1]
Progress: Parameterizing module tick_timer
Progress: Adding tophat_uart [fifoed_avalon_uart 9.3.0]
Progress: Parameterizing module tophat_uart
Progress: Adding user_uart [fifoed_avalon_uart 9.3.0]
Progress: Parameterizing module user_uart
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: sopc.ext_flash_controller: Legacy EPCS/EPCQx1 Flash Controller will only be supported in Quartus Prime Standard Edition in the future release.
Warning: sopc.ext_sram_controller: Properties (isMemoryDevice) have been set on interface uas - in composed mode these are ignored
Info: sopc.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: sopc.sys_id: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: sopc.sys_id: Time stamp will be automatically updated when this component is generated.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\Quasonix\projects\transmitter\DTx_Q21\fpga\common\sopc\sopc.qsys --synthesis=VHDL --output-directory=C:\Quasonix\projects\transmitter\DTx_Q21\fpga\common\sopc\sopc\synthesis --family="Cyclone V" --part=5CEFA7U19I7
Progress: Loading sopc/sopc.qsys
Progress: Reading input file
Progress: Adding boot_rom [altera_avalon_onchip_memory2 21.1]
Progress: Parameterizing module boot_rom
Progress: Adding clk [clock_source 21.1]
Progress: Parameterizing module clk
Progress: Adding ext_flash_controller [altera_avalon_epcs_flash_controller 21.1]
Progress: Parameterizing module ext_flash_controller
Progress: Adding ext_sram_bridge [altera_tristate_conduit_bridge 21.1]
Progress: Parameterizing module ext_sram_bridge
Progress: Adding ext_sram_controller [altera_generic_tristate_controller 21.1]
Progress: Parameterizing module ext_sram_controller
Progress: Adding fpga_interrupt [altera_avalon_pio 21.1]
Progress: Parameterizing module fpga_interrupt
Progress: Adding fpga_io [altera_merlin_slave_translator 21.1]
Progress: Parameterizing module fpga_io
Progress: Adding int_sram [altera_avalon_onchip_memory2 21.1]
Progress: Parameterizing module int_sram
Progress: Adding jtag_uart [altera_avalon_jtag_uart 21.1]
Progress: Parameterizing module jtag_uart
Progress: Adding nios2 [altera_nios2_gen2 21.1]
Progress: Parameterizing module nios2
Progress: Adding pa_uart [fifoed_avalon_uart 9.3.0]
Progress: Parameterizing module pa_uart
Progress: Adding stamp_timer [altera_avalon_timer 21.1]
Progress: Parameterizing module stamp_timer
Progress: Adding sys_id [altera_avalon_sysid_qsys 21.1]
Progress: Parameterizing module sys_id
Progress: Adding tick_timer [altera_avalon_timer 21.1]
Progress: Parameterizing module tick_timer
Progress: Adding tophat_uart [fifoed_avalon_uart 9.3.0]
Progress: Parameterizing module tophat_uart
Progress: Adding user_uart [fifoed_avalon_uart 9.3.0]
Progress: Parameterizing module user_uart
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: sopc.ext_flash_controller: Legacy EPCS/EPCQx1 Flash Controller will only be supported in Quartus Prime Standard Edition in the future release.
Warning: sopc.ext_sram_controller: Properties (isMemoryDevice) have been set on interface uas - in composed mode these are ignored
Info: sopc.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: sopc.sys_id: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: sopc.sys_id: Time stamp will be automatically updated when this component is generated.
Info: sopc: Generating sopc "sopc" for QUARTUS_SYNTH
Warning: sopc: "No matching role found for user_uart:s1:dataavailable (dataavailable)"
Warning: sopc: "No matching role found for user_uart:s1:readyfordata (readyfordata)"
Warning: sopc: "No matching role found for tophat_uart:s1:dataavailable (dataavailable)"
Warning: sopc: "No matching role found for tophat_uart:s1:readyfordata (readyfordata)"
Warning: sopc: "No matching role found for pa_uart:s1:dataavailable (dataavailable)"
Warning: sopc: "No matching role found for pa_uart:s1:readyfordata (readyfordata)"
Info: boot_rom: Starting RTL generation for module 'sopc_boot_rom'
Info: boot_rom: Generation command is [exec C:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/21.1/quartus/bin64/perl/lib -I C:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/21.1/quartus/sopc_builder/bin -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=sopc_boot_rom --dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0045_boot_rom_gen/ --quartus_dir=C:/intelfpga/21.1/quartus --verilog --config=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0045_boot_rom_gen//sopc_boot_rom_component_configuration.pl --do_build_sim=0 ]
Info: boot_rom: Done RTL generation for module 'sopc_boot_rom'
Info: boot_rom: "sopc" instantiated altera_avalon_onchip_memory2 "boot_rom"
Info: ext_flash_controller: Starting RTL generation for module 'sopc_ext_flash_controller'
Info: ext_flash_controller: Generation command is [exec C:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/21.1/quartus/bin64/perl/lib -I C:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/21.1/quartus/sopc_builder/bin -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_epcs_flash_controller -- C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_epcs_flash_controller/generate_rtl.pl --name=sopc_ext_flash_controller --dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0046_ext_flash_controller_gen/ --quartus_dir=C:/intelfpga/21.1/quartus --verilog --config=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0046_ext_flash_controller_gen//sopc_ext_flash_controller_component_configuration.pl --do_build_sim=0 ]
Info: ext_flash_controller: Done RTL generation for module 'sopc_ext_flash_controller'
Info: ext_flash_controller: "sopc" instantiated altera_avalon_epcs_flash_controller "ext_flash_controller"
Info: ext_sram_bridge: "sopc" instantiated altera_tristate_conduit_bridge "ext_sram_bridge"
Info: ext_sram_controller: "sopc" instantiated altera_generic_tristate_controller "ext_sram_controller"
Info: fpga_interrupt: Starting RTL generation for module 'sopc_fpga_interrupt'
Info: fpga_interrupt: Generation command is [exec C:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/21.1/quartus/bin64/perl/lib -I C:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/21.1/quartus/sopc_builder/bin -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=sopc_fpga_interrupt --dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0048_fpga_interrupt_gen/ --quartus_dir=C:/intelfpga/21.1/quartus --verilog --config=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0048_fpga_interrupt_gen//sopc_fpga_interrupt_component_configuration.pl --do_build_sim=0 ]
Info: fpga_interrupt: Done RTL generation for module 'sopc_fpga_interrupt'
Info: fpga_interrupt: "sopc" instantiated altera_avalon_pio "fpga_interrupt"
Info: fpga_io: "sopc" instantiated altera_merlin_slave_translator "fpga_io"
Info: int_sram: Starting RTL generation for module 'sopc_int_sram'
Info: int_sram: Generation command is [exec C:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/21.1/quartus/bin64/perl/lib -I C:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/21.1/quartus/sopc_builder/bin -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=sopc_int_sram --dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0050_int_sram_gen/ --quartus_dir=C:/intelfpga/21.1/quartus --verilog --config=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0050_int_sram_gen//sopc_int_sram_component_configuration.pl --do_build_sim=0 ]
Info: int_sram: Done RTL generation for module 'sopc_int_sram'
Info: int_sram: "sopc" instantiated altera_avalon_onchip_memory2 "int_sram"
Info: jtag_uart: Starting RTL generation for module 'sopc_jtag_uart'
Info: jtag_uart: Generation command is [exec C:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/21.1/quartus/bin64/perl/lib -I C:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/21.1/quartus/sopc_builder/bin -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=sopc_jtag_uart --dir=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0051_jtag_uart_gen/ --quartus_dir=C:/intelfpga/21.1/quartus --verilog --config=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0051_jtag_uart_gen//sopc_jtag_uart_component_configuration.pl --do_build_sim=0 ]
Info: jtag_uart: Done RTL generation for module 'sopc_jtag_uart'
Info: jtag_uart: "sopc" instantiated altera_avalon_jtag_uart "jtag_uart"
Info: nios2: "sopc" instantiated altera_nios2_gen2 "nios2"
Info: pa_uart: Starting FIFOed UART Generation
Info: pa_uart: exec perl -I . -I C:/intelfpga/21.1/quartus/sopc_builder/bin/ -I C:/intelfpga/21.1/quartus/sopc_builder/bin//europa/ -I C:/intelfpga/21.1/quartus/sopc_builder/bin//perl_lib/ mk_em_uart_sa.pl --_system_directory=C:/Users/tomlee/AppData/Local/Temp/alt9191_8059952516168592179.dir/0052_sopcgen/ --language=verilog --name=sopc_pa_uart --clock_freq=93333300 --use_tx_fifo=1 --use_rx_fifo=1 --baud=57600 --data_bits=8 --fixed_baud=0 --parity=N --stop_bits=1 --use_cts_rts=0 --use_eop_register=0 --sim_true_baud=0 --fifo_export_used=0 --Has_IRQ=1 --hw_cts=0 --trans_pin=0 --fifo_size_tx=16 --fifo_size_rx=16 --use_timout=0 --timeout_value=4 --rx_IRQ_Threshold=1 --tx_IRQ_Threshold=1 --tx_fifo_LE=0 --rx_fifo_LE=0 --use_gap_detection=0 --gap_value=4 --use_timestamp=0 --use_ext_timestamp=0 --timestamp_width=8 --add_error_bits=0
Error: pa_uart: couldn't execute "perl": no such file or directory
while executing
"exec perl -I . -I C:/intelfpga/21.1/quartus/sopc_builder/bin/ -I C:/intelfpga/21.1/quartus/sopc_builder/bin//europa/ -I C:/intelfpga/21.1/quartus/sopc..."
("eval" body line 1)
invoked from within
"eval $exec_list"
(procedure "generate" line 70)
invoked from within
"generate"
Error: pa_uart: Generation callback did not provide a top level file (expected `add_file $output_dir/sopc_pa_uart.v|vhd|sv {SIMULATION SYNTHESIS}`)
Info: pa_uart: "sopc" instantiated fifoed_avalon_uart "pa_uart"
Error: Generation stopped, 12 or more modules remaining
Info: sopc: Done "sopc" with 21 modules, 12 files
Error: qsys-generate failed with exit code 1: 3 Errors, 7 Warnings
Info: Finished: Create HDL design files for synthesis

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2022-7-19 Solved on my own:
Found location of perl.exe (C:\intelFPGA\21.1\quartus\bin64\perl\bin), added it to system path variable, restarted Quartus.

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