Quartus Gate Level Simulation mismatch with RTL Simulation

[Anonymous]

Altera Board: DE0 Nano SOC

Xilinx Board: Nexys 4 DDR

I have implemented some RISC-V cores in VHDL and SystemVerilog based on Gaisler VHDL and uploaded to Github repositories:

https://github.com/taneroksuz/riscv-w7.git

https://github.com/taneroksuz/riscv-z0.git

I have tested both designs on Xilinx Vivado 2020.2 Web Edition and I get correct results from behavioural as well as post-synthesis simulation. But Quartus Prime Lite Edition gives me corrupted results on Gate Level Simulation that does not match RTL Simulation. Quartus didn't send no reasonable Warnings or Errors related to both designs.

For both design I have generated PLL (with IP-Core) to run them with desired clock speed. In my case they were 25 MHz (clk_pll) and 1MHz (rtc). These files were not included into repositories. So you have to generate them yourself. The Quartus specific files are located either in folder /vhdl/quartus or /verilog/quartus.

I would like to ask whether this problem arise because of some license issue, that some features not included in lite edition of Quartus or it's just only algorithm issue that would be fixed in future releases of Quartus.

Thanks for your response.

[RichardTanSY_Intel]

Hi ,

Sorry for the delay in response. Do you still need help on this? 

Have you check whether the timing is clean in your design? 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

[RichardTanSY_Intel]

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.