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Hello All,
I have been riding the struggle bus on trying to implement a carry skip adder (carry bypass adder) utilizing a ripple carry chain with multiplexers. I have attached my circuit design below, hopefully it is good enough to read. My issue is that I have no idea what parameters each MUX is to be set to. The (ab) inputs are simple binary 0 or 1 depending on the sum of each ripple. I have also attached the compilation report. If anyone can help I would be grateful and I Thank You in advance. http://www.alteraforum.com/forum/attachment.php?attachmentid=10379&stc=1Link Copied
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The pictures are far to small to see anything.
Is there any reason you are using schematics rather than HDL? Do you have a testbench for this code (you can covert your design to HDL, then simulate).
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