Quartus II V12: .sdo files not generated or in nonexistent folder...don't know which.

[Altera_Forum]

Hello, 

 Under Quartus II V12 Build 178, 5CEBA7U19C8 Cyclone V, VHDL, I cannot get any .sdo files. SR10872286   1. under "Assignments>settings>Simulation>More EDA Netlist Writer Settings"I do not have “generate netlist for functional simulation only” selected. (this would have blocked .sdo generation)   2. I'm following  ftp://ftp.altera.com/up/pub/altera_material/10.1/tutorials/using_modelsim.pdf (ftp://ftp.altera.com/up/pub/altera_material/10.1/tutorials/using_modelsim.pdf) section 5.1   3. I search for "sdo" in all the compilation .rpt report files created during successful compilation and find nothing. Should I find anything?   4. Under Assignments>settings>Simulation I set   Output Directory: c:/Where_I_say  but this is always reset to  Output Directory: simulation/modelsim   "simulation/modelsim" is not a valid pathname and I believe that's where my .sdo file is. Definitely a bug in the template.   Has anybody generated .sdo files for Modelsim under Quartus II V12 and have any wisdom on the process?   Thanks.

[Altera_Forum]

By default the SDO files should be in <project_root>\simulation\modelsim. It works for me with 12.0. I use the native link setup in Quatrus and launch modelsim from tools->Run Simulation Tool->Gate Level Simulation.

[Altera_Forum]

Thanks TrueBlue. 

 Yes, in previous versions Quartus generated a simulation/modelsim subdirectory and put .sdo files there. This was my experience also. I need to use V12 to get my PLLs working properly.   With V12 I had to create the <project>simulation/modelsim subdirectory myself and still I see no .sdo file.   Since the tool allows me to define any path and then ignores that path, I'm suspicious the tool is as confused as I am.

[Altera_Forum]

Have you set Assignments->Settings->EDA Tool Settings->Simulation, and in there selected the Tool Name to be ModelSim-Altera? Also check the output directory setting in there.

[Altera_Forum]

Yes, I have tried  

 Toolname: Modelsim-Altera  Toolname: Modelsim (my true target) Format for output netlist: VHDL Output Directory: simulation/modelsim (the default) Output Directory: <my project>simulation/modelsim    I've also ensured that under "More EDA..." I have turned "Generate netlist for functional simulation only" OFF.   summary Output Directory: type_anything_you_like, OK/Apply results in  Output Directory: simulation/modelsim (the default)   and   no directory is created

[Altera_Forum]

OK, the only difference with what I use is that I use Verilog instead of VHDL. By any chance did you install Quartus somewhere other than its default install location? Quatrus has issues if the install path has spaces in it.

[Altera_Forum]

Thanks again...I'm open to theories.  

 My install path is effectively the default...for example here are where the primitive components are.   C:\altera\12.0\quartus\libraries\vhdl\altera_mf   1. I have played with the language and tried Verilog, with the same non-result.   2. I also just now tried [RESET] on the "More EDA...] template, just in case, and still no progress despite successful compilation.   I'm going to revert to V11.2 and see what happens :)

[Altera_Forum]

The penultimate Quartus II cannot synthesize PLLs generated from the latest Megawizard so I'm going to give it a rest to work on my full blown Modelsim test bench Functional-only and revisit when I get an .sdo file some way, somehow.

[Altera_Forum]

Answer (not resolution) to the problem... 

 Warning (11099): Unable to generate the EDA simulation netlist files because the Quartus II software does not currently support post-compilation simulation for the Cyclone V devices.   I had not noticed this warning but in essence it tells me only have functional simulation at our disposal and I don't believe that's enough. Major stepback and rethink on the whole project.

[Altera_Forum]

hmm... well... i have quartus 14.1 with latest patch right now and have similar problems. while checking in compilation report -> EDA Netlist Writer -> generated files, only vo file is generated. not sdo. and in the same report directory but under messages pane it says: "Generated the EDA functional simulation files although EDA timing simulation is chosen" well... that explains why sdo is not generated. 

altera's help site says:  "CAUSE: You attempted to perform a post-compilation timing simulation on the specified device; however, the feature is not supported in the Quartus II software. The Quartus II software generated the post-compilation functional simulation files instead. ACTION: If you want to run post-compilation functional simulation, then set the eda_generate_functional_netlist assignment or turn on the Generate netlist for functional simulation only option in the Quartus II software."   keep your attention on a "specified device" part, altera guys simply did not created timing information for cyclone v.  Quartus II Handbook Volume 3: Verification 2014.12.15 says: "Note: Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level timing simulation is not supported for Arria V, CycloneV, or StratixV devices. Use TimeQuest static timing analysis rather than gate-level timing simulation."  so basically what they are saying is that "if you have timing issues then go ahead and mess with the timequest why are you simulating at all... -simulate only when you know that your timings are 100% healthy" today's market is a cruel place men.... if there is something that a production can cut off from itself to spare expenditures, marketing managers will sniff it down and cut them.  advantage with timing simulation was that you could observe every logic cell, all the input signals, and their timings. and track down right to the output of the logic cell. this is something that timequest will never give you since it tells you delays between registers. not between logic cells. also it was helping to visualize the exact cause of an error. like on the simulation screen you could see all the signals and one of them was becoming red, indicating a timing violation; and observe the errors that followed because of that exact violated signal. eeh those were the days... but they are gone. :( i wanna kill myself. just as i wanted when quartus cancelled their internal simulator. farewell Modelsim's timing simulation... we had spent many sleepless nights together. you fought shoulder to shoulder with me so many battles. you will always stay in our hearts. ;( (<---it's a crying smile)

[Altera_Forum]

Also with Quartus 15 gate-level simulation is not supported for Cyclone V family :(

[Altera_Forum]

don't bet on quartus releases for gate-level support it is altera's new business strategy now. that's why i started studying other manufacturers. things that are getting chopped off with altera still exists with other manufacturers.lack of something may always be filled. but they lack things that altera has :)) so you have to decide what do you need what to loose and what to gain.problem with altera is that they think it's them or nothing. just as my zombified boss says "we have no other option! and will agree on anything that altera offers".altera does not listens to customers, it simply carries it's own business plan. no gate level simulation is a catastrophe! and to do functional simulation between CycloneV and HPS you need to buy external pack from mentor graphics. even if you try to simulate your project with CycloneIV, it won't work because Logic element architecture in Cyclone V is totally different.we are silent on too many things.what happens with altera is our fault. because we will swallow anything they throw at us.

[Altera_Forum]

I'm very disappointed with Cyclone V.  

 - High static power (over 3x than Cyclone IV) - Longer delay in the clock path - High compile times (Q13.1/Cyclone IV was better) - Poor tool support  - no gate-level simulation  - no auto device selected by fitter - ..  Cyclone V seem worse than Cyclone IV.