Quartus II giving me the wrong error?

Altera_Forum · ‎05-19-2010

Hey, uh, first time here, so yeah... bit nervous, but was wondering if someone could help me with this little problem? ._.

I've worked with Verilog and Quartus in the past, but recently stopped due to the weirdest error messages I've ever seen.

Now, bear in mind this is one of my first projects, and in this I've chosen the CPU route. It's not completely complex, but not completely simple. Code is in the attachment.

I've skimmed over it a thousand times, fixed, debugged, and rooted out the stuff that I thought was the cause. Nowhere did I find the mysterious bug. Errors are below:

Info: *******************************************************************

Info: Running Quartus II Functional Simulation Netlist Generation

Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version

Info: Processing started: Tue May 18 20:05:10 2010

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off WK-2B -c WK-2B --generate_functional_sim_netlist

Info: Found 1 design units, including 1 entities, in source file TopLevel.bdf

Info: Found entity 1: TopLevel

Error (10170): Verilog HDL syntax error at WK-2B.v(524) near text ":"; expecting "<=", or "="

Error (10170): Verilog HDL syntax error at WK-2B.v(529) near text "default"; expecting "@", or "end", or an identifier ("default" is a reserved keyword ), or a system task, or "{", or a sequential statement

Error (10170): Verilog HDL syntax error at WK-2B.v(533) near text "endcase"; expecting "@", or "end", or an identifier ("endcase" is a reserved keyword ), or a system task, or "{", or a sequential statement

Error (10170): Verilog HDL syntax error at WK-2B.v(536) near text "end"; expecting "endcase", or an identifier ("end" is a reserved keyword ), or a number, or a system task, or "(", or "{", or unary operator

Info: Found 0 design units, including 0 entities, in source file WK-2B.v

Info: Found 1 design units, including 1 entities, in source file MemoryManager.v

Info: Found entity 1: MemoryManager

Error: Quartus II Functional Simulation Netlist Generation was unsuccessful. 4 errors, 0 warnings

Info: Allocated 164 megabytes of memory during processing

Error: Processing ended: Tue May 18 20:05:11 2010

Error: Elapsed time: 00:00:01

...*Ahem* What?

Please, please tell me, and please point it out if you see it. I don't wanna be bumbling around like an idiot here. X.x

Thanks for the help in advance, much obliged to you all! :)

~JW

Altera_Forum · ‎05-19-2010

Just looking at your code fairly quickly, it appears you are missing the "end" statement for the "if" that begins on line 127. After inserting an "end" statement at line 518, the code compiles.

Altera_Forum · ‎05-19-2010

Thanks. I tried to match up every if statement with it's corresponding begin and end. Looks like I missed one.

Regards,

~JW