HiIn the spec sheet on the MAX V CPLD is says "You can debug your MAX V designs using In-System Sources and Probes Editor in the Quartus II software. This feature allows you to easily control any internal signaland provides you with a completely dynamic debugging environment." But when I try to use the SignalTap II Logic Analyzer in Quartus Prime on a MAX V through a USB Blaster clone I get the message "SignalTap II is not supported for the current device" I am using Quartus Prime Lite running on Ubuntu Linux. What am I missing? If you have any questions or suggestions please let me know. Thanks Roger50310
Is this the case? Signal Tap only supported for FPGAs instead of CPLDs (eg MAX V).
Seen in a Video that ELA only works with FPGA designs and not CPLDs because of the availability of memory in Intel FPGA devices. It stated need available LBs to implement the Logic Analyzer itself + Memory blocks to store/capture data samples.
Was looking today to add signal Tap to check my design but looks like this is not feasible for MAX V device. Please confirm