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Quartus Prime Pro and Questasim

TowerLy
Novice
287 Views

Hi,

I use Quartus Prime Pro and Questasim. I have a basic design that has two modules (counter and PLL IP).  After  Analysis and Elaboration -> Generate Simulator Script for IP, I open Questasim and enter necessary commands to transcript as mentioned in ug-qpp-tp-simulation.pdf. Simulation starts, modules are seen but there is no signal for visibility. For full visibility, I enter "vopt" command but Questasim gave an error that fourteennm_clk_divider.v in PLL IP is not defined. What is wrong that I made?

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2 Replies
EngWei_O_Intel
Employee
237 Views

Hi Samet Caglan

Can you share us the design or at least the design files with issue and the script that you set up?

Thanks.

Eng Wei

 

 

EngWei_O_Intel
Employee
197 Views

Hi 

We do not receive any response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei

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