I use Quartus Prime Pro and Questasim. I have a basic design that has two modules (counter and PLL IP). After Analysis and Elaboration -> Generate Simulator Script for IP, I open Questasim and enter necessary commands to transcript as mentioned in ug-qpp-tp-simulation.pdf. Simulation starts, modules are seen but there is no signal for visibility. For full visibility, I enter "vopt" command but Questasim gave an error that fourteennm_clk_divider.v in PLL IP is not defined. What is wrong that I made?
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