Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17267 Discussions

Quartus Prime Pro internal / unexpected error during fitter floorplan

billmax
New Contributor I
1,364 Views

I first saw this error for Agilex designs under Prime Pro 22.4 and also 23.2.  It is repeatable and seem related to signaltap.  My signaltap nodes are all pre-synthesis, and previously I 'cured' the problem by deleting the latest signaltap changes and adding them again. Now after several design changes and signaltap additions it is happening again. I think I see which nodes it's complaining about and will try to adjust those.  The questionable node(s) shouldn't be available for selection in signaltap, but also shouldn't cause a crash if they are in the .stp file.

 

Example error

Problem Details
Error:
Internal Error: Sub-system: PTI, File: /quartus/tsm/pti/pti_tdb_builder.cpp, Line: 5410
ATOM uut|ddr4_dram_sub|emif_fm_0|emif_fm_0|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst Type: FALCONMESA_TILE_CTRL (atom id 506) with OTERM type O_MMR_OUT[33] does not lead to top-level port when it wants to reach ITERM type DATAIN[0] of ATOM uut|ddr4_dram_sub|emif_fm_0|emif_fm_0|arch|arch_inst|hmc_mmr_if_inst|mmr_slave_waitrequest_1 Type : FALCONMESA_FF (atom id 46363)
Stack Trace:
Quartus 0x125984: PTI_TDB_BUILDER::report_missing_connection_to_top_level_output_port_message + 0x1e0 (tsm_pti)
Quartus 0x1d312: PTI_TDB_BUILDER::get_src_node_for_ic_edge + 0x262 (tsm_pti)
Quartus 0x1d01b: PTI_TDB_BUILDER::create_iterm_ic_edge + 0x45f (tsm_pti)
Quartus 0x1c9b4: PTI_TDB_BUILDER::build_or_update_tdb_netlist + 0x348 (tsm_pti)
Quartus 0x4ac5d: PTI_DELAY_ANNOTATOR::full_annotate_routing_and_cell + 0x575 (tsm_pti)
Quartus 0x4b28e: PTI_DELAY_ANNOTATOR::build_multicorner + 0x4b2 (tsm_pti)
Quartus 0xdab16: FITCC_TDC_UTILITY::initialize_dat + 0x1296 (fitter_fitcc)
Quartus 0xdbdb2: FITCC_TDC_UTILITY::setup_tdc_utility + 0x1d2 (fitter_fitcc)
Quartus 0xd6d1e: FITCC_TDC_UTILITY::FITCC_TDC_UTILITY + 0xde (fitter_fitcc)
Quartus 0x805b4: FITCC_ENV::get_tdc_utility_or_create_if_necessary + 0x464 (fitter_fitcc)
Quartus 0x80e23: FITCC_ENV::get_tdc_utility_or_create_if_necessary + 0x143 (fitter_fitcc)
Quartus 0x80f45: FITCC_ENV::get_tdc_utility_or_create_if_necessary + 0x95 (fitter_fitcc)
Quartus 0x8fd6d: FSAC_FF_REGISTER_PACKER_OP::perform_timing_analysis + 0x8d (FITTER_FSAC)
Quartus 0x13f185: FDRGN_REGISTER_PACKER::do_packing + 0x215 (fitter_fdrgn)
Quartus 0x74faf: fdrgn_post_plan_ops + 0x64f (fitter_fdrgn)
Quartus 0x26412: fit2_fit_plan + 0x622 (comp_fit2)
Quartus 0x16442: TclNRRunCallbacks + 0x62 (tcl86)
Quartus 0x17c4d: TclEvalEx + 0x9ed (tcl86)
Quartus 0xa6a8b: Tcl_FSEvalFileEx + 0x22b (tcl86)
Quartus 0xa5136: Tcl_EvalFile + 0x36 (tcl86)
Quartus 0x22460: qexe_evaluate_tcl_script + 0x640 (comp_qexe)
Quartus 0x21062: qexe_do_tcl + 0x8c2 (comp_qexe)
Quartus 0x2a1d1: qexe_run_tcl_option + 0x701 (comp_qexe)
Quartus 0x2d2d6: QCU::DETAIL::intialise_qhd_and_run_qexe + 0x116 (comp_qcu)
Quartus 0x3dfcb: qcu_run_tcl_option + 0x76b (comp_qcu)
Quartus 0x2994e: qexe_run + 0x61e (comp_qexe)
Quartus 0x2ac84: qexe_standard_main + 0x264 (comp_qexe)
Quartus 0xbc22: qfit2_main + 0x82 (quartus_fit)
Quartus 0x277b8: msg_main_thread + 0x18 (ccl_msg)
Quartus 0x28772: msg_thread_wrapper + 0x82 (ccl_msg)
Quartus 0x2ac13: mem_thread_wrapper + 0x73 (ccl_mem)
Quartus 0x25415: msg_exe_main + 0x175 (ccl_msg)
Quartus 0xcdaf: __scrt_common_main_seh + 0x10b (quartus_fit)
Quartus 0x17613: BaseThreadInitThunk + 0x13 (KERNEL32)
Quartus 0x526a0: RtlUserThreadStart + 0x20 (ntdll)

End-trace


Executable: quartus
Comment:
None

System Information
Platform: windows64
OS name: Windows 10
OS version: 10.0.19044

Quartus Prime Information
Address bits: 64
Version: 23.2.0
Build: 94
Edition: Pro Edition

 

Screenshot

screenshot.1671.jpg

 

Usage under previous successful compilation

Fitter Status : Successful - Fri Jul 7 15:55:51 2023
Quartus Prime Version : 23.2.0 Build 94 06/14/2023 SC Pro Edition
Revision Name : bw_ia840f
Top-level Entity Name : bw_ia840f_top
Family : Agilex 7
Device : AGFB027R25A2E2V
Timing Models : Final
Power Models : Final
Device Status : Final
Logic utilization (in ALMs) : 75,498 / 912,800 ( 8 % )
Total dedicated logic registers : 211714
Total pins : 664 / 886 ( 75 % )
Total block memory bits : 10,669,308 / 271,810,560 ( 4 % )
Total RAM Blocks : 893 / 13,272 ( 7 % )
Total DSP Blocks : 0 / 8,528 ( 0 % )
Total HSSI P-Tiles : 1 / 2 ( 50 % )
Total HSSI E-Tile Channels : 0 / 24 ( 0 % )
Total HSSI HPS : 0 / 1 ( 0 % )
Total HSSI EHIPs : 0 / 4 ( 0 % )
Total PLLs : 13 / 36 ( 36 % )

Labels (1)
0 Kudos
5 Replies
CosmoKramer
Employee
1,341 Views

I am having similar issue. atom id and line number in the cpp file are different but reset is similar. please let me know if you find a solution to this. I tried looking at logs but the atom id is no where present. error message is not very helpful and is very cryptic. 

0 Kudos
RichardTanSY_Altera
1,330 Views

I could not find this internal error in our database. Could you help to share your design .qar file (Project> Achieve Project) that could duplicate this error?

We will need to duplicate the error as without the error duplication from our side, it would be hard to find a workaround/solution.

This will requires the engineering team to investigate on this and please keep in mind that any work involving our engineering team may take some time, ranging from a few days to a few weeks, depending on the complexity of the issue.

Thank you for your understanding.


Best Regards,

Richard Tan



0 Kudos
RichardTanSY_Altera
1,296 Views

Hi,


Any update on this? Do you able to share your design?


Best Regards,

Richard Tan


0 Kudos
billmax
New Contributor I
1,276 Views

I'm unable to share a design at this time.  I don't have an archive of the design before I removed signaltap nodes to fix it. If it occurs again I will submit one.

0 Kudos
RichardTanSY_Altera
1,252 Views

Noted. Since there is no design available for duplication of the issue, we are unable to proceed with debugging it further.


Therefore, I will transition this thread to community support. If you have any additional questions or concerns, please feel free to reach out.

Thank you, and have a great day!


Best Regards,

Richard Tan


p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey. 


0 Kudos
Reply