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15334 Discussions

Quartus Prime Standard Edition v17.0 Error: add_fileset_file: No such file

Altera_Forum
Honored Contributor II
1,158 Views

Hi, 

 

I'm facing error in Qsys while generating NIOS system with "create simulation model" = either verilog or vhdl, no error if "create simulation model" = NONE. 

Does anyone know what is causing this error? 

 

Thanks. 

https://alteraforum.com/forum/attachment.php?attachmentid=14441&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14442&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14443&stc=1  

 

Error: add_fileset_file: No such file /tmp/alt7491_7829365739350634514.dir/0006_cpu_gen/simgen_tmp_0 

while executing 

"add_fileset_file "$file_name" OTHER PATH "$my_file"" 

(procedure "sub_add_generated_files" line 51) 

invoked from within 

"sub_add_generated_files "$NAME" "$output_directory" "$rtl_ext" "$simgen" "$plainTEXTfound"" 

(procedure "generate_with_plaintext" line 6) 

invoked from within 

"generate_with_plaintext "$NAME" "$rtl_ext" "$simgen"" 

(procedure "sub_sim_verilog" line 5) 

invoked from within 

"sub_sim_verilog nios_nios2_gen2_0_cpu" 

Error: Generation stopped, 33 or more modules remaining 

Error: qsys-generate failed with exit code 1: 2 Errors, 0 Warnings
0 Kudos
6 Replies
Altera_Forum
Honored Contributor II
263 Views

Are you using the fast version of the processor? Do you have a license for the fast version?

Altera_Forum
Honored Contributor II
263 Views

 

--- Quote Start ---  

Are you using the fast version of the processor? Do you have a license for the fast version? 

--- Quote End ---  

 

 

yes, I'm using NIOS II/f, Qsys is able to generate synthesis files but not simulation files, seems not license issue.  

 

And Qsys Pro can generate both the simulation and synthesis files. 

 

Thanks.
Altera_Forum
Honored Contributor II
263 Views

Can you try following. 

 

1. Try generating the testbench for same project and see if you face similar Error ? 

Qsys menu 

Generate > Generate Testbench System 

 

2. Use the NIOs system from AN351 and see if you can generate the simulation file  

https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios... 

 

 

3. Also try newer version of Quartus Prime 17.1 ? 

 

Best Regards, 

arslanusman2003 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor II
263 Views

Hi, 

 

1. I tried "Generate Testbench System", as long as "Create Simulation Model" is Verilog or VHDL, generation failed. 

2. Same failure.  

3. It will take some time to install 17.1, I have tried v16 with same error. Quartus II v13.1 has no issue. 

 

Thanks.
Altera_Forum
Honored Contributor II
263 Views

Hi Terry, 

 

It is working fine with Quartus prime Standard Edition. 

Recheck steps and license. OR reinstall the quartus.  

 

Refer attached image in word document  

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

Altera_Forum
Honored Contributor II
263 Views

Hi Anand, 

 

I will try v17.1 and get back.  

 

Thanks for your support.
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