Quartus Prime (Verilog) Error (10200): Verilog HDL Conditional Statement error

[HypeInst]

I desire to interface an FPGA to a 32-bit ADC. The serial clock to the ADC should be gated and only clock the ADC after the ADC has finished acquiring each sample. I am gating the serial clock by means of a counter (pulse_count) that counts the 32-bits for each sample and then disables the clock until the ADC reports that the next sample is ready (when the busy signal goes low). The following is the Verilog code for the block that enables/disables the serial clock to the ADC:

always_ff @(posedge clk, negedge busy, negedge reset_n) begin
  if (!reset_n) enable_ADC_clk <= 1'b0;
 
  else if (pulse_count == 5'b01111) enable_ADC_clk <= 1'b0;

  else enable_ADC_clk <= 1'b1;
end

Upon synthesis, I receive the following Quartus Prime (Lite) error message:

Error (10200): Verilog HDL Conditional Statement error at filename.sv(line-number cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct.

Quartus Prime (Lite) appears to insist that pulse_count, which tracks the current number of bits out of the ADC, must be in the sensitivity list. However, I'm confused as to why that's necessary. Additionally, I cannot think of an alternative approach.

Please advise.

[ak6dn · Accepted solution]

Remove negedge busy from the always_ff sensitivity list, and add logic tests for busy == 1'b0 in the appropriate if statements to only clock the data on posedge clk when busy is low, else hold data otherwise.

You are telling Quartus that data can change on either posedge clk or negedge busy which can't happen for a single clock flipflop.

[HypeInst]

Thank you for your response!