always_ff @(posedge clk, negedge busy, negedge reset_n) begin if (!reset_n) enable_ADC_clk <= 1'b0; else if (pulse_count == 5'b01111) enable_ADC_clk <= 1'b0; else enable_ADC_clk <= 1'b1; end
Upon synthesis, I receive the following Quartus Prime (Lite) error message:
Error (10200): Verilog HDL Conditional Statement error at filename.sv(line-number
Quartus Prime (Lite) appears to insist that pulse_count, which tracks the current number of bits out of the ADC, must be in the sensitivity list. However, I'm confused as to why that's necessary. Additionally, I cannot think of an alternative approach.