Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Quartus Pro 21.1 emif IP generation for Agilex device fails

KolosKoblasz
Beginner
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Dear Community!

In platform designer I would like to construct a HPS system which uses DDR4 memory.
After instantiating and customizing the necessary modules the HDL generation fails.

Error: couldn't open "/usr/local/altera/21.1/ip /altera/emif/ip_arch_fm/fw_src//iossm_qii_sim.hex": no such file or directory
Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings
Error: SPD file was not generated: /home/kolos/Projects/agilex_sloth/src/ip/ip/hps/hps_emif_cal_0/hps_emif_cal_0.spd
Error: Could not generate simulation scripts
Error: couldn't open "/usr/local/altera/21.1/ip /altera/emif/ip_arch_fm/fw_src//iossm_qii_sim.hex": no such file or directory
Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings

As you can see the highlighted parts of some paths contain extra white spaces which does not exist in the reality.
Can you suggest a solution to convince Quartus Pro 21.1 to use the correct paths?

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