Quartus-Questa Compilation Simulation Dependency Management

[skim3]

Hello,

I had a question about dependency management using Quartus and Questa.

For a FPGA project that I'm working on, I noticed that when I do Tools->Run Simulation->RTL Simulation, a .do file gets generated, with vlog commands with the systemverilog/library/package files that need to get compiled. However, when trying to use it to run vsim commands in Questa, I noticed that some files were failing to include each other, and when going through the .do file, I noticed that some dependencies were not properly resolved (eg. a package would be compiled after the systemverilog file that tries to import it).

For other softwares, I'm aware of functions such as smartorder for Xcelium and autoorder for Modelsim which takes care of dependency ordering. 

Is there a feature similar to autoorder from Modelsim in Questa? If so, how can I implement it?

Thank you

[RichardTanSY_Altera]

I believe you are using Quartus Standard Edition and attempting to simulate using the Nativelink simulation flow.

Typically, when we run Tools → Run Simulation → RTL Simulation, the Quartus Standard Edition software automatically launches the Questa Altera Edition simulator and simulates the testbench file according to the specifications set in the Simulation settings.

I have not encountered any dependency ordering issues when using Nativelink.

Does the issue occur when you try to execute the .do file manually during simulation?

For example:

do PLL_RAM_run_msim_rtl_verilog.do

You may want to try running the example design (quartus-std-lite-pll-ram) provided in the user guide, following the steps and guidance described in the document.

Lite/Standard Edition:

https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html

Regards,

Richard Tan

[skim3]

Hello Richard,

Thank you for your suggestion. I followed through the sample design, and it seems to work, so I am discarding the possibility that this is a Nativelink issue. 

While going through the error messages, I noticed that quite a few of them were about missing cxl-related packages, such as cxlip_top_pkg. As described in my other ticket (Re: Inquiry about device support for AGIB027R29A1E2VR3 in Quartus Prime Pro v25.1.0 - Intel Community), I am currently experiencing another difficulty with the IP Core CXL IP for Device Type 2 with Device Coherency (6AF7 0185) not getting recognized as licensed in the Assembler stage of the Compilation Flow.

If an IP is not fully recognized as licensed, could it also act as a possible source of missing package errors in Questa Nativelink simulation flow?

Many thanks,

[working]

The architectural detailing is top notch, and the textures give it a very realistic and polished look. It’s clear a lot of thought went into both the design and presentation. I really appreciate that you’ve included both the baked and non baked texture versions makes it versatile for different projects and rendering needs. Thanks for sharing such a high quality 3D model with the community.

[RichardTanSY_Altera]

As I mentioned in another post, this CXL IP has specific limitations, such as not supporting SOF/POF generation. I believe the same restriction applies to simulation as well.

To my knowledge, this IP is unique in that regard. You should be able to evaluate other IPs without encountering the same limitation.

Edit: For evaluation license, simulation, compilation, & timing of CXL IP are enabled. Limitation with (no .sof/.pof generation).

Regards,

Richard

[skim3]

Hello Richard, 

Thank you for your feedback. I took a closer look at the directories in my project and conducted more research online, and the issue seemed to be more related to the dependency order for compiled packages/included files in the .do file, and less related to the CXL IP license. 

Before running the Nativelink flow, I've included all files that are used in my project in the Quartus Pro project's .qsf file. And while checking the .do file, I noticed that the order of files in .qsf and .do are exactly the same. 

From the messages in the Questa terminal, it seems that the files included with `include statements are parsed without any error. 

e.g.) vlog -sv -work work +incdir+/root/CHMU/ASPLOS-2025-M5-main_VERSION000/hw/r1bes_mmio/r1bes_mmio/hardware_test_design/common/mc_top+/root/CHMU/ASPLOS-2025-M5-main_VERSION000/hw/r1bes_mmio/r1bes_mmio/hardware_test_design/ {/root/CHMU/ASPLOS-2025-M5-main_VERSION000/hw/r1bes_mmio/r1bes_mmio/hardware_test_design/common/mc_top/axi2avmm_bridge.sv}

However, the files included as packages, if listed in the .do file after the file that is including it, always gives an error.

e.g.) # ** Error: /root/CHMU/ASPLOS-2025-M5-main_VERSION000/hw/r1bes_mmio/r1bes_mmio/hardware_test_design/common/cm_sketch_sorted_cam/afu_banking/src/hot_tracker_top.sv(9): (vlog-13006) Could not find the package (mc_axi_if_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.

• Is it that for `include files, +incdir+ command takes care of the dependency order, but for packages, the packages need to be explicitly compiled before any and all files that try to refer to it?
• Is there a way to get either Quartus or Questa to automatically detect dependencies and produce a re-ordered .do file (no matter the file listing order in .qsf file)? Or do I have to manually order my package files in .qsf and/or .do?

Thank you for your time.

[skim3]

Update: I tried re-ordering the files in the .qfs according to the dependencies that were implied in the error messages in the Word file attached above, but I received a very similar set of error messages, still regarding could not find the package (package_name).

[RichardTanSY_Altera]

I might need to access the project to further debug the issue.

Could you share your design by archiving the project (Project > Archive Project) so that I further investigate.

Regards,

Richard Tan

[skim3]

I appreciate your offer for help.

However, the project file is unfortunately too big, and when I tried to split it up using 7zip, the first part of the split file could not be uploaded to the forum. If you could provide a separate link for the file to be submitted to, that would be great. 

If that is not possible, as I'm simply trying to implement and simulate a public project from GitHub without modifications for now, I can share the GitHub site here as well: GitHub - ece-fast-lab/ASPLOS-2025-M5: This is the respository that holds the artifacts of ASPLOS'25 -- M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems

From the GitHub repo, I've been testing with the testbench file that can be found in the directory:

ASPLOS-2025-M5/hw/m5_rtl/r1bes_mmio/hardware_test_design/common/cm_sketch_sorted_cam/cm_sketch/sim/cm_sketch_tb_random.sv

Best regards,

[RichardTanSY_Altera]

I will share your a site to upload the project. Please check your email shortly.

Regards,

Richard Tan

[skim3]

Hello Richard,

Due to time differences and the 4th of July weekend, I only checked the email today. Due to maintenance work going on at work, I cannot access my QAR file immediately. I will share it with you as soon as the maintenance work is over and let you know.

Thank you for your kind offer, and my apologies for the delay.

Best,

[skim3]

Hello Richard,

I just realized that when I uploaded the file last Friday, you must have been out of office as it would have been Saturday in Malaysia time. I re-uploaded the file today, so please let me know if you have received it.

Best regards,

[skim3]

Hello Richard,

I uploaded the files to the site you have shared with me. Thank you for providing an alternative means of sharing the file with you.

Best regards,

[skim3]

Hello Richard,

I re-uploaded the files to the site. Please let me know if you need anything else.

Best regards,

[RichardTanSY_Altera]

I’ve received the design, but it appears to be in Quartus Pro 25.1. Could you confirm if that’s correct?

I’m asking because we were discussing NativeLink simulation in the previous replies, which is a feature not supported in Quartus Pro.

Regards,

Richard Tan

[skim3]

Hello Richard,

Thank you for your insight. I reflected on my HDL simulation workflow, and I realized that I haven't been using correct terminology in our conversation.

- I'm using Quartus Prime Pro v25.1, which when I checked, doesn't support NativeLink simulation flow.
- The simulation flow I've been using is the following. While it is not NativeLink, I believe it follows the suggested simulation flow with Quartus Prime Pro:
1. Register all design files (including IPs) in the Quartus Prime Pro project by selecting [ Project menu > Add/Remove Files in Project ]

2. Set the path for EDA tool executable program in [ Tools > Options > EDA tool options ]

3. Set board and IP settings in [ Assignments > Settings > Board and IP settings ]

4. Set simulation settings in [ Assignments > Settings > EDA Tool Settings > Simulation ]

5. Register test bench in [ Assignments > Settings > EDA tool settings > Simulation > Testbench ]

6. Generate simulation scripts for IP by selecting [ Tools > Generate simulator setup script for IP ]

Following through these steps (sometimes in different order) and running [ Tools > Run Simulation > RTL Simulation ] created a .do file which I ran with Intel Questa FPGA Edition, where I experienced compilation errors relating to missing package files (which were listed in the .do file).

What confused me about troubleshooting is the following:
- I tried this Intel tutorial, which worked even on Quartus Prime Pro, so I'm assuming that [ Tools > Run Simulation > RTL Simulation ] might not have been the issue (https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html)
- Some package files are not being found when compiling in Intel Questa FPGA Edition, even though they are present at the directories mentioned in the .do file

For my project (which involves several IPs), should I have used the scripted flow instead, as recommended in the links below? (I've found several Macnica support links handy, though they had to be translated into English from Japanese)
https://www.macnica.co.jp/en/business/semiconductor/articles/intel/133550/ 
https://www.macnica.co.jp/en/business/semiconductor/articles/intel/146968/ 
https://www.intel.com/content/www/us/en/docs/programmable/730191/25-1/commands-to-compile-elaborate-and-simulate.html 

I apologize for some confusion in the use of terminology.

[skim3]

Hello Richard,

Thank you for your response. Please understand I'm replying to your email via this thread because my work email (which I'm using for this account) doesn't allow me to send emails outside of organization. 

While I can't try the simulation immediately due to server maintenance at work, I can try simulating with Questa (I don't have VCS) early next week and follow up with you. My manager has been discussing the license-related issue with Intel personnel, so I'm not clear on all details, but I will clarify with him as well.

Best,

[RichardTanSY_Altera]

Noted. I’ll reply in this thread if the email content does not contain any confidential information. e.g. INI/UG

If there is any confidential information that cannot be shared in the forum, I will respond via email instead.

Thank you for your understanding.

Regards,

Richard

[willamabroy2]

Use Quartus for synthesis and generate simulation files, then import them into Questa. Manage dependencies with correct file paths and library mappings in the simulation setup.

[RichardTanSY_Altera]

Hi,

Any update on this?

Do you able to run the CXL IP simulation using the supported simulator tool - Questasim (not Intel FPGA Edition)?

Regards,

Richard Tan

[RichardTanSY_Altera]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

The community users will be able to help you on your follow-up questions.

Thank you for reaching out to us!

Best Regards,

Richard Tan