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Altera_Forum
Honored Contributor I
1,269 Views

Quartus VHDL-2008 outdated IEEE package ?

Hi, 

I'm using Quartus 16.1.2 and it seem to use outdated package for IEEE.std_logic_1164 and IEEE.numeric_std because I can't use the Unary Reduction Logic Operators provide by VHDL-2008. 

example: ack <= or(ack_vector); 

https://alteraforum.com/forum/attachment.php?attachmentid=15251&stc=1  

Does anyone know how fix this issue?  

 

Note: Work with Vivado and Questa Sim
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7 Replies
Altera_Forum
Honored Contributor I
368 Views

It's not outdated. Quartus only supports a few features of vhdl 2008. 

 

Quartus pro has full vhdl 2008 support
Altera_Forum
Honored Contributor I
368 Views

Crap 

Cyclone V 5CGXFC5 doesn't seem to be supported in PRO :(
Altera_Forum
Honored Contributor I
368 Views

Afaik, Pro only supports 10 series and onwards, and comes at extra cost.

Altera_Forum
Honored Contributor I
368 Views

The work around is to use the synopsys std_logic_misc library and use the or_reduce function: 

 

use ieee.std_logic_misc.all; ack <= or_reduce(ack_vector);
Altera_Forum
Honored Contributor I
368 Views

Work 

thank you :)
NBerg1
Beginner
368 Views

Are there any plans fro generally supporting VHDL-2008 in the Standard Quartus anyime soon?

JC_FPGA
Novice
153 Views

I just came across this thread in a search.  It's been three years since this thread was created and the OR reduction operator is still not supported in Quartus Prime Standard Edition.  It works fine when I simulate in Questa.

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