Hi,I'm using Quartus 16.1.2 and it seem to use outdated package for IEEE.std_logic_1164 and IEEE.numeric_std because I can't use the Unary Reduction Logic Operators provide by VHDL-2008. example: ack <= or(ack_vector); https://alteraforum.com/forum/attachment.php?attachmentid=15251&stc=1 Does anyone know how fix this issue? Note: Work with Vivado and Questa Sim
The work around is to use the synopsys std_logic_misc library and use the or_reduce function:
use ieee.std_logic_misc.all; ack <= or_reduce(ack_vector);
I just came across this thread in a search. It's been three years since this thread was created and the OR reduction operator is still not supported in Quartus Prime Standard Edition. It works fine when I simulate in Questa.