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Hello,
I'm attempting to make my own RISC V processor, and part of that is selecting the correct OPCode, I have the following VHDL which is supposed to do this:
--/-----------------------------\
--| OPCODE INSTRUCTION DECODING |
--\-----------------------------/
with fetched_instruction select?
next_decoded_opcode <=
LB when "-----------------000-----00000--",
LH when "-----------------001-----00000--",
LW when "-----------------010-----00000--",
LBU when "-----------------100-----00000--",
LHU when "-----------------101-----00000--",
SB when "-----------------000-----01000--",
SH when "-----------------001-----01000--",
SW when "-----------------010-----01000--",
BEQ when "-----------------000-----11000--",
BNE when "-----------------001-----11000--",
BLT when "-----------------100-----11000--",
BGE when "-----------------101-----11000--",
BLTU when "-----------------110-----11000--",
BGEU when "-----------------111-----11000--",
JALR when "-------------------------11001--",
JAL when "-------------------------11011--",
Addi when "-----------------000-----00100--",
SLLI when "-----------------001-----00100--",
SLTI when "-----------------010-----00100--",
SLTIU when "-----------------011-----00100--",
XORI when "-----------------100-----00100--",
ORI when "-----------------110-----00100--",
ANDI when "-----------------111-----00100--",
SRLI when "-0---------------101-----00100--",
SRAI when "-1---------------101-----00100--",
ADD when "-0---------------000-----01100--",
SUB when "-1---------------000-----01100--",
inst_SLL when "-----------------001-----01100--",
SLT when "-----------------010-----01100--",
SLTU when "-----------------011-----01100--",
inst_XOR when "-----------------100-----01100--",
inst_SRL when "-0---------------101-----01100--",
inst_SRA when "-1---------------101-----01100--",
inst_OR when "-----------------110-----01100--",
inst_AND when "-----------------111-----01100--",
AUIPC when "-------------------------00101--",
LUI when "-------------------------01101--",
CSRRS when "-----------------010-----11100--", -- NEEDS IMPLEMENTATION--
CSRRW when "-----------------001-----11100--", -- NEEDS IMPLEMENTATION--
CSRRC when "-----------------011-----11100--", -- NEEDS IMPLEMENTATION--
CSRRSI when "-----------------110-----11100--", -- NEEDS IMPLEMENTATION--
CSRRWI when "-----------------101-----11100--", -- NEEDS IMPLEMENTATION--
CSRRCI when "-----------------111-----11100--", -- NEEDS IMPLEMENTATION--
INVALID when others;
However, even though inside Quartus, the file is marked as a VHDL2008 file, synthesis still fails, citing that:
"Error (10500): VHDL syntax error at controller.vhd(159) near text "?"; expecting "(", or an identifier, or a string literal"
The above statement synthesizes completely fine within Xilinx's Vivado, so I'm not quite sure what Quartus is trying to see that Vivado can handle.
Why is Quartus having issues with the 'select?' clause, and what can I do to remedy this while maintaining the syntax (eg: I still want to use with/select? and have the wildcards available for easy reading)
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It may also be prudent to note that the 'case when' syntax using wildcards is also broken:
--/-----------------------------\
--| OPCODE INSTRUCTION DECODING |
--\-----------------------------/
case? fetched_instruction is
when "-----------------000-----00000--" =>
next_decoded_opcode <= LB;
when "-----------------001-----00000--" =>
next_decoded_opcode <= LH;
when "-----------------010-----00000--" =>
next_decoded_opcode <= LW;
when "-----------------100-----00000--" =>
next_decoded_opcode <= LBU;
when "-----------------101-----00000--" =>
next_decoded_opcode <= LHU;
when "-----------------000-----01000--" =>
next_decoded_opcode <= SB;
when "-----------------001-----01000--" =>
next_decoded_opcode <= SH;
when "-----------------010-----01000--" =>
next_decoded_opcode <= SW;
when "-----------------000-----11000--" =>
next_decoded_opcode <= BEQ;
when "-----------------001-----11000--" =>
next_decoded_opcode <= BNE;
when "-----------------100-----11000--" =>
next_decoded_opcode <= BLT;
when "-----------------101-----11000--" =>
next_decoded_opcode <= BGE;
when "-----------------110-----11000--" =>
next_decoded_opcode <= BLTU;
when "-----------------111-----11000--" =>
next_decoded_opcode <= BGEU;
when "-------------------------11001--" =>
next_decoded_opcode <= JALR;
when "-------------------------11011--" =>
next_decoded_opcode <= JAL;
when "-----------------000-----00100--" =>
next_decoded_opcode <= Addi;
when "-----------------001-----00100--" =>
next_decoded_opcode <= SLLI;
when "-----------------010-----00100--" =>
next_decoded_opcode <= SLTI;
when "-----------------011-----00100--" =>
next_decoded_opcode <= SLTIU;
when "-----------------100-----00100--" =>
next_decoded_opcode <= XORI;
when "-----------------110-----00100--" =>
next_decoded_opcode <= ORI;
when "-----------------111-----00100--" =>
next_decoded_opcode <= ANDI;
when "-0---------------101-----00100--" =>
next_decoded_opcode <= SRLI;
when "-1---------------101-----00100--" =>
next_decoded_opcode <= SRAI;
when "-0---------------000-----01100--" =>
next_decoded_opcode <= ADD;
when "-1---------------000-----01100--" =>
next_decoded_opcode <= SUB;
when "-----------------001-----01100--" =>
next_decoded_opcode <= inst_SLL;
when "-----------------010-----01100--" =>
next_decoded_opcode <= SLT;
when "-----------------011-----01100--" =>
next_decoded_opcode <= SLTU;
when "-----------------100-----01100--" =>
next_decoded_opcode <= inst_XOR;
when "-0---------------101-----01100--" =>
next_decoded_opcode <= inst_SRL;
when "-1---------------101-----01100--" =>
next_decoded_opcode <= inst_SRA;
when "-----------------110-----01100--" =>
next_decoded_opcode <= inst_OR;
when "-----------------111-----01100--" =>
next_decoded_opcode <= inst_AND;
when "-------------------------00101--" =>
next_decoded_opcode <= AUIPC;
when "-------------------------01101--" =>
next_decoded_opcode <= LUI;
when "-----------------010-----11100--" =>
next_decoded_opcode <= CSRRS; -- NEEDS IMPLEMENTATION--
when "-----------------001-----11100--" =>
next_decoded_opcode <= CSRRW; -- NEEDS IMPLEMENTATION--
when "-----------------011-----11100--" =>
next_decoded_opcode <= CSRRC; -- NEEDS IMPLEMENTATION--
when "-----------------110-----11100--" =>
next_decoded_opcode <= CSRRSI; -- NEEDS IMPLEMENTATION--
when "-----------------101-----11100--" =>
next_decoded_opcode <= CSRRWI; -- NEEDS IMPLEMENTATION--
when "-----------------111-----11100--" =>
next_decoded_opcode <= CSRRCI; -- NEEDS IMPLEMENTATION--
when others =>
next_decoded_opcode <= INVALID;
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You don't indicate which version of Quartus (Lite, Standard, or Pro) you are using, but VHDL2008 is not supported in Lite. The supported 2008 features in Pro are listed here:
TBH, I'm trying to understand what the ? there does and the only paragraph I can find in the standard that describes it (section 10.5.4) is a little vague:
"If a selected signal assignment statement includes the question mark delimiter, then the equivalent sequential statement includes a question mark delimiter after both occurrences of the reserved word case; otherwise the equivalent sequential statement does not include the question mark delimiters."
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Interesting, One can select VHDL 2008 in the lite edition, I assume that it is vestigial. One can read more about the ? artifact here: https://www.doulos.com/knowhow/vhdl/vhdl-2008-small-changes/
Tl;DR: it allows wildcards in the when statements.
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I'm not sure what happened to my other message, I'm sure I wrote them...
One can read more on the 2008-VHDL ? artifact here: https://www.doulos.com/knowhow/vhdl/vhdl-2008-small-changes/
Tl;DR: It allows the used of wildcards in select / case / when statements.
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Hi,
May I know which software edition you are using?
Thanks
Best regards,
KhaiY
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Hi,
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
Thanks
Best regards,
KhaiY
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