Quartus crashes on 'elaborating entity'

[CZHE0]

I'm seeing a crash when I instantiate a module. I have checked that the module itself compiles/synthesizes just fine. I did an experiment, which is to instantiate only this module, and I already see the crash. I also tried putting the instantiated module in a separate file, but that didn't help either. Below is some more info. What did I do wrong?

Quartus message output:

Info: Running Quartus Prime Analysis & Synthesis

Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition

Info: Processing started: Thu Dec 05 10:09:06 2019

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex_8_8_str -c ex_8_8_str

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected

Info (12021): Found 4 design units, including 4 entities, in source file controller.sv

Info (12023): Found entity 1: controller

Info (12023): Found entity 2: d_ff

Info (12023): Found entity 3: mux_4x1

Info (12023): Found entity 4: dec_2x4

Info (12021): Found 1 design units, including 1 entities, in source file controller_elab.sv

Info (12023): Found entity 1: controller_elab

Info (12021): Found 1 design units, including 0 entities, in source file ex_8_8_pkg.sv

Info (12022): Found design unit 1: ex_8_8_pkg (SystemVerilog)

Info (12127): Elaborating entity "controller_elab" for the top level hierarchy

Info (12128): Elaborating entity "controller" for hierarchy "controller:cntlr_0"

Crash report:

Problem Details

Error:

*** Fatal Error: Access Violation at 0X00007FF98CAA4306

Module: quartus_map.exe

Stack Trace:

0xb4305: Netlist::ProcessGlobals + 0x3b5 (synth_vrfx)

0xb2675: Netlist::Polish + 0x95 (synth_vrfx)

0xef5ea: VeriModule::Elaborate + 0x62a (synth_vrfx)

0x70b1a: VRFX_VERIFIC_VERILOG_ELABORATOR::elaborate + 0x6da (synth_vrfx)

0x69bb7: VRFX_ELABORATOR::elaborate + 0xd7 (synth_vrfx)

0xdab8f: SGN_FN_LIB::elaborate + 0x24f (synth_sgn)

0xe37bf: SGN_FN_LIB::start_vrf_flow + 0xf (synth_sgn)

0xe1d9b: SGN_FN_LIB::start + 0xa1b (synth_sgn)

0xc294a: SGN_EXTRACTOR::single_module_extraction + 0x15a (synth_sgn)

0xb7524: SGN_EXTRACTOR::recursive_extraction + 0x204 (synth_sgn)

0xb6e6f: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist + 0x36f (synth_sgn)

0xb757b: SGN_EXTRACTOR::recursive_extraction + 0x25b (synth_sgn)

0xb08c3: SGN_EXTRACTOR::extract + 0x1d3 (synth_sgn)

0x1324e: sgn_qic_full + 0x19e (synth_sgn)

0x4351: qsyn_execute_sgn + 0x131 (quartus_map)

0x13f9c: QSYN_FRAMEWORK::execute_core + 0x12c (quartus_map)

0x13aa6: QSYN_FRAMEWORK::execute + 0x496 (quartus_map)

0x112bc: qexe_do_normal + 0x1ec (comp_qexe)

0x16142: qexe_run + 0x432 (comp_qexe)

0x16e51: qexe_standard_main + 0xc1 (comp_qexe)

0x1b08b: qsyn_main + 0x51b (quartus_map)

0x12e98: msg_main_thread + 0x18 (CCL_MSG)

0x1467e: msg_thread_wrapper + 0x6e (CCL_MSG)

0x16660: mem_thread_wrapper + 0x70 (ccl_mem)

0x12761: msg_exe_main + 0xa1 (CCL_MSG)

0x29872: __tmainCRTStartup + 0x10e (quartus_map)

0x14033: BaseThreadInitThunk + 0x13 (KERNEL32)

0x73690: RtlUserThreadStart + 0x20 (ntdll)

End-trace

Executable: quartus_map

Comment:

None

System Information

Platform: windows64

OS name: Windows 10

OS version: 10.0

Quartus Prime Information

Address bits: 64

Version: 18.1.0

Build: 625

Edition: Lite Edition

Top level hierarchy:

import ex_8_8_pkg::*;   module controller_elab ( input rstb, clk, start, zero, msb, output rdy, load_regs, shift_left, incr_r2 ); controller cntlr_0 ( .rstb(rstb), .clk(clk), .start(start), .zero(zero), .msb(msb), .rdy(rdy), .load_regs(load_regs), .shift_left(shift_left), .incr_r2(incr_r2) ); endmodule

Controller module:

import ex_8_8_pkg::*;   module controller ( input rstb, clk, start, zero, msb, output logic rdy, load_regs, shift_left, incr_r2 ); logic G0, D0_in, D1_in, G1; wire zero_b = ~zero, msb_b = ~msb; wire [1:0] sel = {G1, G0}; logic [0:3] dec_out; assign rdy = ~dec_out[0], incr_r2 = ~dec_out[1], shift_left = ~dec_out[2], load_regs = rdy & start;   mux_4x1 mux_1 (sel, GND, zero_b, PWR, msb_b, D1_in); mux_4x1 mux_0 (sel, start, GND, PWR, msb, D0_in); d_ff dff_1 (rstb, clk, D1_in, G1); d_ff dff_0 (rstb, clk, D0_in, G0); dec_2x4 dec_0 (G1, G0, GND, dec_out); endmodule   module d_ff ( input rstb, clk, D, output logic Q ); always_ff @ (posedge clk, negedge rstb) begin if (!rstb) Q <= 1'b0; else Q <= D; end endmodule   module mux_4x1 ( input [1:0] sel, input in_0, in_1, in_2, in_3, output m_out ); always_comb begin case (sel) 2'b00 : m_out = in_0; 2'b01 : m_out = in_1; 2'b10 : m_out = in_2; 2'b11 : m_out = in_3; endcase end endmodule   module dec_2x4 ( input A, B, enable_b, output [0:3] D ); assign D[0] = ~(~A & ~B & ~enable_b), D[1] = ~(~A & B & ~enable_b), D[2] = ~(A & ~B & ~enable_b), D[3] = ~(A & B & ~enable_b); endmodule

Package:

package ex_8_8_pkg; parameter st_width = 3; typedef enum logic [st_width-1:0] {S0, S1, S2, S3} state_t; parameter r1_size = 8, r2_size = 4; supply0 GND; supply1 PWR; endpackage

[sstrell]

Try using the Clean Project command from the Project menu and/or closing your project and deleting the db and incremental_db directories from your project directory. Then try compiling again.

#iwork4intel

[CZHE0]

@sstrell​ I have tried 'Clean Project' and deleting the 'db' folder, but it did not help. I couldn't find any 'incremental_db' directories.

[KhaiChein_Y_Intel]

Hi,

Can you provide the design.qar for investigation, Project > Archive Project > Archive ?

Thanks.

[CZHE0]

I have attached the qar file for my project.

[CZHE0]

FYI I think I have found the issue but I do not know why. It seems synthesis does not like the fact that I put this in a package:

supply0 GND; supply1 PWR;

If I take this out of the package and declare directly in the controller module, then it works.

[KhaiChein_Y_Intel]

Hi,

I will file a case to engineering team. Thanks for reporting this to us.

Thanks.

[KhaiChein_Y_Intel]

Hi,

Below is the reply from the team:

After doing some debugging on this case, a workaround that I can suggest is

to use different names other than GND and PWR in your run. I see a lot of referencing

to those two names in Verific code, which might cause the issue you are reporting.

So in ex_8_8_pkg.sv, you can do this:

     supply0 GND0;

     supply1 PWR1;

then in your controller.sv file, use the new names: GND0, PWR1 in the MUX AND dec instances.

Your run should complete without errors.

Can you try it and let me know fi this work for you.

Thanks.

[CZHE0]

I have tried renaming GND to GND0 and PWR to PWR1, but I did not see any difference and still get a crash. Attached another archive with the update.

[KhaiChein_Y_Intel]

Hi,

I am sorry for the delay in response as I was out of office last week.

Please allow me some time to consult the team.

Thanks

[KhaiChein_Y_Intel]

Hi,

Upon checking, the Intel Quartus Prime Standard edition software has limited support in declaring globals in package file. Please comment out those two lines from ex_8_8_pkg.sv

Thanks.