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ZAhma1
Beginner
605 Views

Quartus error 13223 during synthesis on IP file generated by Quartus

I am porting a design from Quartus 16.1 to Quartus 19.2. I've followed the user guide and have cleared most warnings and errors and upgraded IP files.

 

One of the IPs generated by Quartus fails to load during synthesis and I get error 13223 "cannot open vhdl file" or "cannot open verilog file". The files are there and access permissions are OK. I can open the files and it looks like they're encrypted. But they should still be readable by Quartus, seeing as it generated them.

 

The help file is not very useful for this error code.

 

"ACTION: Edit the file to correct the error. A future version of the Quartus Prime software will provide more detailed information about this error."

 

I cannot edit an encrypted file. Is there any real solution to this problem?

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8 Replies
226 Views

Hi Zahma,

 

Can you try to specify the path of your verilog file in the qpf file. Suspect quartus does not able to find the path for the verilog file

set_global_assignment -name VERILOG_FILE XX.v

 

Btw, do you mind to share your design so that I can replicate the error and understand more

 

Thanks

Joanne

ZAhma1
Beginner
226 Views

Hi Joanne,

 

I tried using a manual set_global_assignment as you said, but it did not work.

 

I then tried to create a new empty project with the same device, and only add the ip file for the failing block. I see the same issue here too. I've attached the project to this message. Please take a look and let me know.

 

Thanks!

--Zohair

226 Views

​Hi Zahma,

 

I am able to run the compilation using quartus version 19.1 without getting the error above.

 

When I run the design using quartus 19.2, I am not able to replicate the error as you mention. But I get the ' Error(16368): Top-level design entity "test_191" is undefined '

So, I change the setting in the .qsf file  and generate HDL of the IP using platform designer

set_global_assignment -name TOP_LEVEL_ENTITY fft_ii_2048

May I know is this your top level file?  

 

 

Attached is the design file

 

Thanks

Joanne

 

ZAhma1
Beginner
226 Views

Hi Joanne,

 

I tried again with your archive. But I still get the same error 13223. For reference I'm using Quartus Prime 19.2. I've attached a screenshot of the about page for version info.

226 Views

​Hi I am using same quartus version as your. Is this possible to share me the design .qar file Btw, do you able to open those Verilog file using file tab in quartus? Can you remove those Verilog file in the error and add again Thanks Joanne
226 Views

Hi, Any updates in this thread? Thanks Joanne
ZAhma1
Beginner
226 Views

Hi Joanne,

 

Apologies but I was unable to look into this over the last two days.

 

So far I have tried

 

* Open the files in Quartus (using File->open)

** For this I get an error "Can't open encrypted file"

 

* Add failing files to project. (Project -> Add remove files)

** Same output ("cannot open vhdl file... ")

 

* Updated license server files according to this workaround: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/...

** Same output ("cannot open vhdl file... ")

 

So far no change in the output. I've attached the project file here.

 

Thanks!

--Zohair

ZAhma1
Beginner
226 Views

Hi Joanne,

 

I've spoken with our Intel rep and we've found that there is something wrong with our license files. We were sent a test license to check and with that we are able to compile correctly. We are now investigating what's wrong with our license files.

 

I think this issue can be closed since this is not an issue with the tools themselves.

 

Thanks for your help!

--Zohair

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