Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Quartus : error in compilation

kikoss
New Contributor I
285 Views

Hello 

 

I receive the following error in compilation : 

 

Error(16812): Verilog HDL error at safety_top_level.sv(178): port connections cannot be mixed ordered and named. Or there might be a trailing comma in named port connection.

 

what can be wrong here ?

kikoss_0-1716908695681.png

 

Thx

Kikoss

 

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sstrell
Honored Contributor III
271 Views

You don't say which line is line 178, but you're missing a dot in front of rx_in_p.

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sstrell
Honored Contributor III
272 Views

You don't say which line is line 178, but you're missing a dot in front of rx_in_p.

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kikoss
New Contributor I
268 Views

THX!

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