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APack
Beginner
1,387 Views

Quartus ignoring delay/skew constraints but not giving a warning

Hi, I am using Quartus 15.0.2 (just before prime came in) and a cyclone 5CGX.

 

I am trying to do clock reconstruction using a data and strobe line (both pins into the FPGA) this obviously requires a minimizing of skew but I've tried two different approaches and both times it appears to have just been ignored but not thrown an error.

 

The commands were put in an .sdc file that is definitely being used ( it's the one that defines the clocks and they are being picked up) so I'm a bit lost as what is happening.

 

I am using the set_max_skew but also tried set_max_delay and set_min_delay. An example command is below

 

set_max_skew -from {sbr_sbn[8], dbr_dbn[8]} -to [get_cells {typ_ntwrk_ctrl_fpga_top_inst|typhoon_endpoint_inst|\gen_endpoint_xN:Router_Uod_1|\ports:8:Spwr_Network_Link_1|spwrlinkwrap_1|spwrlink_1|rxclock_1|RX_CLK}] 1.0

 

I can't see anything wrong with the syntax and it doesn't report there as being anything.

 

Any help would be appreciated

 

 

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3 Replies
59 Views

Hi,

 

Kindly remove the comma between sbr_sbn[8] and dbr_dbn[8]?

You may test the constraint in TimeQuest TCL console. Do you see any error message?

 

Thanks.

APack
Beginner
59 Views

Does the comma not delineate the 2 ports I'm trying to constrain? I tried removing it and rebuilding and once again has had no effect, I tried in timequest and got no errors for either syntax but when building using them in the .sdc file they appear to take no effect and there is no mention of them in the console

59 Views

You may report 'Ignored Constraints' and see if this constraint is being ignored. Also, you can report 'Report Max Skew' to see the details of this constraint.

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