Quartus not detecting FPGA through USBIP

[maguena]

I have a setup of one main computer running Ubuntu 20 and Linux kernel 6.0.6, and one DE0-CV board connected by USB to a Raspberry Pi Model 3B+ running a fresh install of Raspbian. I've installed USBIP on both the computer and the Raspberry, so I could program the FPGA remotely.

However, it seems Quartus cannot read the board for some reason. Every time I run jtagconfig --enum, it returns:

1) USB-Blaster [6-2]

    Unable to read device chain - Hardware not attached

When I try to upload any project to the board though Quartus, it fails, stating that the hardware can't be selected.

If I connect the board directly to the computer, then Quartus does recognizes it and allows me to program it. However, I want to be able to do this remotely.

I'm sure the connection does work, since I've also connected an USB stick to the Raspberry and accessed it from the computer through USBIP while trying to access the FPGA.

Since I've done a fresh install of Raspbian and compiled the USBIP project directly from the Linux repository at Github in both machines, I don't think there are problems at the Raspberry side, though I can't rule out this possibility entirely...

Has anyone tried this before? Any ideas or tips?

[YuanLi_S_Intel]

From the explanation, it seems like there is something wrong with the connection between raspberry Pi & the FPGA thus the device cannot be detected. First of all, how do you connect the Pi with the FPGA? Secondly, is the FPGA hardware designed created by your own or from the github?

[maguena]

Greetings,

The FPGA board is a Terasic DE0-CV without any modifications, completely brand new. It gets connected to the Raspberry Pi through the USB cable included in the box (it has an onboard USB Blaster, with an USB type B port). It can also be connected to the computer this way.

[YuanLi_S_Intel]

Since the signal is coming from raspberry Pi. I would suggest to check from that side, at least if there is any signal to the on-board USB Blaster on the FPGA. Secondly, is on the github design whether the design is suitable for your case. This is what i can think off. Hope it helps.

[YuanLi_S_Intel]

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.