I'm trying to synthesize a Verilog into Cyclone V.
However, compilation does not proceed in 11% of Analysis & Synthesis.
An error message will be displayed when the synth size is 11% and the maximum machine memory capacity is 134GB.
The error message says it adheres to Quartus' memory requirements, but it has 134GB of machine memory.
Why does it consume 134GB against the memory requirement of 6GB for Cyclone V?
Is there a way to find out which source code is leaking memory during compilation?
Quartus: Quartus Prime SE 20.1.1 Build 720
Error Message :
Error (293007): Current module quartus_map ended unexpectedly. Verify that you have sufficient memory available to compile your design. You can view disk space and physical RAM requirements on the System and Software Requirements page of the Intel FPGA website (http://dl.altera.com/requirements/).
only software cpu core IP and Normal compilation.
machine memory : 134GB
disk space : 2TB available