Quartus simulator timing warnings

[Altera_Forum]

Hi all, 

 I'm a newbie to CPLDs but have compiled a few systems on Quartus ready for programming. I have had warnings displayed about clock skew and latching errors but I can't resolve these by changing anything in my designs. Using the timing analyzer just throws up loads of figures which I'm unsure of the impact on the final circuit designs. My question is this. If my circuit is using only a fairly low frequency external clock of less than 500kHz, would these warnings make much difference to the functionality of the final chip? :)

[Altera_Forum]

Hi, 

 clock skew and latching issues are serious. Your Fmax wouldn't help. Fmax is only a security against Tsu violations(setup time for flipflops), it does not help with hold time violations. You must make sure you have no timing problems reported.

[Altera_Forum]

I have removed 2 gated clocks and used clock enables instead on the relevant counters. I suspect that some of the problems may be due to using data synchronizing latches and some half period clock-derived pulses. As I have only one clock for the entire circuit, if I make this my global clock, would this improve delay problems? BTW I am using timing analyzer as opposed to classic timing.

[Altera_Forum]

I would have thought that using only one clock might help things. If you've still got problems then you can try using multicycle holds to tell Quartus that the clock enables don't change every clock cycle and so on those paths the clock frequency is effectively lower. 

 Check the help on that - I've not done it for a while.  Have you set the required clock frequency to your 500kHz? If you only want the device to run that fast then there's precious little point in forcing Quartus to make it work faster.  Also look at the paths that cause the biggest problem - i.e. the longest delay between registers. If you've got a big lump of combinatorial logic then try pipelining it a bit.