Quartus synthesis constrain

[Altera_Forum]

Hi, 

 In my project, the following code was to delay the data, I want to use the logic elements to implement in fpga, but the Quartus automatically use altshift_taps to implement which will cost one M9K.  Does there any constrains to constrain it using logic elements?   Thanks,  FPGA: EP3C40 QUARTUS II 8.1   -- -- delay the input data -- pes_ua_array(0) <= pes_ua; pes_ua_fs_array(0) <= pes_fs_ua;  pes_ua_delay:   for i in 1 to 13 generate    process(rst,clk)  begin  if (rst = '1') then  pes_ua_array(i) <= (others=>'0');  pes_ua_fs_array(i) <= '0';  elsif (clk'event and clk = '1') then  if (pes_v_ua = '1') then  pes_ua_array(i) <= pes_ua_array(i-1);  pes_ua_fs_array(i) <= pes_ua_fs_array(i-1);  end if;  end if;  end process;    end generate;

[Altera_Forum]

Hi, 

 This might be helpful  http://quartushelp.altera.com/10.0/mergedprojects/hdl/vhdl/vhdl_file_dir_attribute.htm (http://quartushelp.altera.com/10.0/mergedprojects/hdl/vhdl/vhdl_file_dir_attribute.htm)  As an example it shows the use of the AUTO_SHIFT_REGISTER_RECOGNITION attribute. Which it looks like you'll need to set to OFF  Hope this helps  Vern

[Altera_Forum]

Hi Vern, 

 Thank you very much!  Synthesis Attribute is what I need.  Regards,  HXD