Hi all,
i want to change my VHDL project adding a new VHDL module. How can I do this? P.S. I've already the .bdf file, so how can I use it to add my new VHDL module in the project? Thanks a lot. Lorenzo連結已複製
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open the VHDL file in quartus. Make sure the source code is added to the project file list.
goto File -> Create/update -> Create symbol file. Then in your top level BDF double click anywhere and now your modules should be available to place in the BDF. NOTE: You cannot simulate BDF files directly. You have to either convert them to HDL or compile them for a (slow) netlist simulation. The best option is just to make the whole design HDL.