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typedef struct {
int unsigned size_of_smth;
etc. etc.;
} param_t;
localparam param_t PARAMS =
`{
size_of_smth : 4,
etc : ....
};
typedef logic [PARAMS.size_of_smth - 1 : 0] smth;
Quartus shows the following error:
Error (10742): Verilog HDL error at some_file.svh(12): constant expression cannot contain a hierarchical identifier
PARAMS.size_of_smth is a constant, so I think it should be supported
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Hi,
I'm using two versions:
Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
and
Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Full Version
Both of them produce the same error
Thanks,
Siarhei
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Hi,
I apologize for the overlook on this case. We had an internal transition issue and the engineer overlooked this case on his plate. May I know if your request still outstanding? I can then decide on the next course of action for this case. Thank you.
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Hi,
I found workaround. But I think this issue requires attention.
Thanks.
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Thank you for letting me know. Would you mind explaining to me what the workaround was? I can use that information for the verification at my end before I submit a ticket to engineering for the bug fixing or enhancement.
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Hi,
can you provide two design.qar for us?
1) design.qar that can replicate the error
2) design.qar that had your workaround
Thanks,
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Thanks for your input. I will feedback this to the engineering.
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