I know that it's possible to compile VHDL files to different libraries.
Is it possible to do the same with Verilog?
Is it possible the different compilation libraries will have the same package/module names?
May I know what is different libraries here and which libraries do you mean?
Based on my understanding, there is no library in verilog but you can use Verilog header file that can allow you to do some component functionality.
You can write a verilog file and then include it in another verilog file. In this verilog file, you might instantiate the component used. You may try the code as stated in link below:
Cannot I use the 'vlog -work <libname> <filename>' command in order to compile the <filename> file into <libname> library?
The situation is so that I have a design with two modules, which have the the same name but a different functionality and they are located in the different hierarchies of the design...
So, I'm seeking a way how to compile the design without touching the files... So I thought that compiling the design into the different libraries could give a solution...
Based on my understanding, with the tcl script mentioned above: "vlog -work <libname> <filename>" can
only used pre-compile the library and verilog file in ModelSim in third party simulation process.
May I know that do you want to do compilation design file with libraries in ModelSim or Quartus?
Also, may I know the reason of the module with the same name but it is different hierarchies and functionality.