I am trying to collect data from signal tap by using quartus_stp from command line. However, I always get "JTAG communcation error. Check hardware setup".
When i attempt to collect data from the same design using GUI of signaltap it aquires data normally. Can you help me solve this issue ?
The tcl script I use is as follows:
open_session -name test.stp
run -instance auto_signaltap_0 -data_log test1-timeout 500
export_data_log -data_log test1-filename test1.csv -format csv
I wrote this in a test.tcl
then in windows cmd, I called
quartus_stp -t test.tcl
I get "JTAG Communication Error. Check hardware setup"
I used a different version of Signal tap and I got this message
Internal Error: Sub-system: SDR, File: /quartus/sld/sdr/sdr_data_log.cpp, Line: 789
this->m_trigger_pos >= 0 && this->m_trigger_pos < samples_allocated
So i concluded that the trigger happens too early before enough samples are collected. I changed the trigger to a 19-bit counter. The trigger happened when the counter is equal to FFFF.
The previous error disappeared. However, I did a for loop to continously cature data from embedded logic and I received the data log with half the samples X and the rest of the samples are 0, except for the counter values which are increasing.
Any idea what is happening ?
Another general question on how signal tap works, if the triger condition is reached, would the embedded logic analyzer stop aquiring new data?or Does the RAM content that is transferred via JTAG remain constant till the trigger condition is repeated again ? I am trying to know the reason behind the data I get to solve the issue.