Questa intel FPGA has no delay to Gate level simulation

[hokagechichi]

I used Cyclone IV (EP4CE6E22C8), and the delay should be 9ns. However, my Gate level simulation's delay was 0. What should I do?

[sstrell]

It doesn't look like you are running a gate-level sim.  It looks like a standard RTL sim.

[SyafieqS]

That seem to be rtl simulation. And also, it is always better to use sta for timing instead gate level for timing.

[SyafieqS]

Let me know if there is any update

[hokagechichi]

https://www.youtube.com/watch?v=7KO9uHGxEOI
This Showed the steps I executed gate level simulation

[AEsqu]

Maybe you need to synthesize the RTL first?

[FvM]

I'm missing the step where you import the gate level netlist.

[hokagechichi]

Finally, I found that I should turn off "Generate functional simulation netlist", then the gate level simulation will display correctly.

ref:  https://www.youtube.com/watch?v=HFWd7QPibMY&t=400sh

Thank to everyone.

[SyafieqS]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 5/5 survey