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QuestaSim and CycloneV PLL:flat output

明张0002
Beginner
333 Views

Hello everyone,

I am tried to use the 'PLL_Reconfig_MNC.qar' example in AN661 on Altera PLL and Altera PLL Reconfig IP core of the Cyclone V,but I failed.When I simulating at Questasim,clock outputs from the pll stay at a value of '1' and it doesn't lock.

What makes it tricky is that I scan simulate the IP which contains the pll with a testbench and everthing works fine.But when this IP is placed in the example design it doesn't work.

What is puzzling is when I tried to use Arria 10 or Cyclone IV instead of Cyclone V in the example design,it works fine. ALL the above simulate are generated in Queartus Prime17.1 IP core,and then independently simulated with QuestaSim.Does  Queartus Prime17.1 not support pll reconfig of CycloneV?

 

as you can see,output clocks stay flat.pllreconfig.png

 

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1 Reply
RichardTanSY_Intel
137 Views

Hi, please allow me some time to work on your request. I will get back to you as soon as possible.

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