Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Question regarding partitions

Altera_Forum
Honored Contributor II
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Hi, 

During the last few days I have been seperating my design into different partitions and generating qxp files to import into the top level project with the aim of making the existing code unviewable to another team. 

 

Anyway I have successfully achieved this and upon compilation I receive over 900 warnings, telling me that I should register each I/O from each of the partitions and avoid assigning the same clk to differnt clk pins etc, as optimizations cannot be performed between partitions. Anyway I don´t want to make these changes, as it implies quite a few changes to the code will be quite time consuming. 

 

I was hoping someone could let me know if there was a way to achiveve what i want to achiveve (making the code unviewable) without being forced into making these code changes. 

 

Also, when Quartus produces the warning regarding registering I/O´s of the partitions, I understand that it is only a recomendation to symplify complience with timing, and that if the design meets timing then it is not a nessesery step. Is this a correct assumption? 

 

Many thanks for any advice
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Altera_Forum
Honored Contributor II
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Your assumption is correct. Almost nobody registers everything between partitions. I wouldn't worry about it unless you suddenly start failing timing when bringing them all together. (The change in synthesis is generally not too bad at all, so it would mean you have paths crossing partitions that barely make timing. I would address those individual paths if you see them failing timing later on, rather than worry about it now.)

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Altera_Forum
Honored Contributor II
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Thanks for the reply Rysc. 

Just one more thing. I also receive warnings regarding the partitions:  

 

-Connecting or removing unused ports  

 

-Avoid driving multiple ports of a partition with the same signal, i.e. the same clock for a rd and wr clk of a DC FIFO 

 

From what I understand, the only disadvantge here is that the design would use up more resouces in the FPGA than it would if the partitions interfaces could be optimized. Please confirm that my thinking on this is ok and that these 900 warnings are really nothing to get alarmed about? 

 

Many thanks for the help
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Altera_Forum
Honored Contributor II
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Correct. All I/O are kept for partitions. This allows the user to "hook them up later" without resynthesizing/fitting the existing partition.

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