/RESET signal in VHDL

[Altera_Forum]

Hi to all 

In order to use VHDL Z80 and external VDP I need to build a /RESET signal. I've tried this code :    --- Quote Start ---  library ieee;use ieee.std_logic_1164.all; entity TB_RST is port (  RESET_N : out std_logic  ); end TB_RST;  architecture BIDULE of TB_RST is  begin   RESET_N <= '0', '1' after 10 ns, '0' after 30 ns;  end BIDULE;  --- Quote End ---    The problem is that : when I compile with /RESET as input pin all is good but if I use this code the compiler show 0% like reset_n never change state

[Altera_Forum]

Of course, that is not synthesizable. 

You need to use a clock and a counter to generate a reset.

[Altera_Forum]

I'm back with this. 

I think it works , my led is on / off /on  library IEEE; use IEEE.STD_LOGIC_1164.ALL;  entity reset is  Port (  clk_in : in STD_LOGIC;  reset_n: out STD_LOGIC  ); end reset;  architecture Behavioral of reset is  signal temporal: STD_LOGIC:='1';  signal cycle: integer range 0 to 2 := 0;  signal counter : integer range 0 to 10000000 := 0; begin  frequency_divider: process (clk_in) begin    if rising_edge(clk_in) then  if (counter = 10000000) and (cycle /= 2) then  temporal <= NOT(temporal);  counter <= 0;   cycle <= cycle + 1;  else  counter <= counter + 1;  end if;  end if;  end process;    reset_n <= temporal; end Behavioral;  Now I need to find good time for a valid /RESET signal.