I am using Quartus II Web Edition ver. 13. I am just starting out. I am trying to simulate the following VHDL code:
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-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition"
-- CREATED "Fri Feb 08 14:19:36 2019"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY test IS
PORT
(
b : IN STD_LOGIC;
a : IN STD_LOGIC;
f : OUT STD_LOGIC
);
END test;
ARCHITECTURE bdf_type OF test IS
BEGIN
f <= a AND b;
END bdf_type;When I run an RTL simulation, I get the following output:
As a close-up of the waveform,
You can see that when b = 1 and a = 0, f = 1. What??
This has also been a problem in my course lab with a slightly more complex circuit. The code seems fine but the RTL simulation is not matching up.
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