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Hi to everybody!!!
When I want to see RTL-representation of VHDL-design I use RTL Viewer. Does anybody know how to get some another representation of RTL, something like netlist but just for RTL-level? I want to make changes in the structure using RTL-representation. Thank you in advance!!!Link Copied
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Have you tried the Quartus Grafical entry files, .bdf?
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Thanks for your reply Tricky, but I need a possibility to change RTL representation of VHDL-design given from RTL Viewer.
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That is not possible, because it would need to back annotate the source code. From the RTL viewer, you can link back to source code though, so that might be a good compromise.
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Ok. Maybe you know, Is there any other format of RTL-represantation, something like EDIF but for RTL?
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You still need to change the source. Hence why the RTL viewer is just a viewer. Why would you want to change the design post synthesis, rather than the source code?
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it is a part of my investigation. ok thank you for your replies.I'll think it over.
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