Reading and Writing Text File in VHDL

[Altera_Forum]

Hi guys. 

  I have tried run this coding. But, it has error. Why it happens? Btw, i refer to this website for the tutorial. http://vhdlguru.blogspot.com/2010/03/reading-and-writing-files-in-vhdl-easy.html . Thanks in advance  --include this library for file handling in VHDL. library std; use std.textio.all; --include package textio.vhd   --entity declaration entity filehandle is end filehandle;   --architecture definition architecture Behavioral of filehandle is --period of clock,bit for indicating end of file. signal clock,endoffile : bit := '0'; --data read from the file. signal dataread : real; --data to be saved into the output file. signal datatosave : real; --line number of the file read or written. signal linenumber : integer:=1;    begin     clock <= not (clock) after 1 ns; --clock with time period 2 ns     --read process reading : process  file infile : text is in "1.txt"; --declare input file  variable inline : line; --line number declaration  variable dataread1 : real;   begin wait until clock = '1' and clock'event; if (not endfile(infile)) then --checking the "END OF FILE" is not reached. readline(infile, inline); --reading a line from the file.  --reading the data from the line and putting it in a real type variable. read(inline, dataread1); dataread <= dataread1; --put the value available in variable in a signal. else endoffile <='1'; --set signal to tell end of file read file is reached. end if;   end process reading;   --write process writing : process  file outfile : text is out "2.txt"; --declare output file  variable outline : line; --line number declaration  begin wait until clock = '0' and clock'event; if(endoffile='0') then --if the file end is not reached. --write(linenumber,value(real type),justified(side),field(width),digits(natural)); write(outline, dataread, right, 16, 12); -- write line to external file. writeline(outfile, outline); linenumber <= linenumber + 1; else null; end if;   end process writing;   end Behavioral;

[Altera_Forum]

This code will not work in quartus, as it is for simulation only.

[Altera_Forum]

Why it cannot work in Quartus? which part that i need to modify. So that, it can be used in Quartus

[Altera_Forum]

File IO is only meant for simulation. So none of the above code is suitable

[Altera_Forum]

Thanks Tricky for your fast reply. If you don't mind, could you explain to me what is the difference between simulation and synthesis? I know there are differences coding for simulation and synthesis. But, I don't understand very well.  

 Thanks in advance :)

[Altera_Forum]

Simulation allows you to test the code you want to deploy 

Synthesis converts your code to hardware blocks. So for FPGAs it maps your code to the base level LUTs, registers, memories, multipliers etc.

[Altera_Forum]

Sorry for the late reply Tricky. 

 I have text file which contain data of my sensitivity map. My sensitivity map contain matrix 64 x 64. I want to load the text file because want to multiply it for my equation. Is it possible?

[Altera_Forum]

In what situation? where does the sensitivity map reside? Is it a LUT, or is it a set of input data for your system?

[Altera_Forum]

Thanks for your fast reply. 

 The text file is a set of my input data for my system.

[Altera_Forum]

Then you can only read the data in simulation. For the real system you need a some real mechanism to get the data into the board.

[Altera_Forum]

Thanks for your fast reply. 

 What kinds of mechanism that I need? sorry for my question. I am beginner for VHDL

[Altera_Forum]

With such a small file, you could probably stick it in a ROM on the chip and put some logic in to play the data out, Or you could send it from a PC.