Report some 2008 generic bug

[IA32]

Hello. I want to report some bugs in the generic part of the std VHDL 2008. I don't know if questa sim is supposed to handle all 2008 feature or just a subset. I had some problem with my code so I've tried to reduce the sample as small as possible.

The first one is a little one. It's deal with case-sensitive feature.

entity Test is
end Test;
architecture Bench of Test is
  function Length(x: in bit_vector) return natural is begin return x'length; end length;
  procedure payload generic (pure function Length(x: in bit_vector) return natural is <>) is begin end payload;
  procedure trigger is new payload;
begin
end Bench;

Here vcom report me: No visible function "Length" to use as default for interface subprogram...

To solve that, I must replace Length for length. Whenever I add an uppercase in the formal generic parameter, I can't use "<>".

And the second one is linked with the option -voptargs="+acc".

context Risc is
  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.numeric_std.all;
end context Risc;

context Work.Risc;
entity Memory is
  generic (Delay_Cycle: positive := 1);
  port (Clk: in std_logic);
end Memory;
architecture RTL of Memory is
  signal Delay: positive;
  procedure Triger_Crash generic (type Unknown) is
    begin end Triger_Crash;
begin
  process (Clk) is
    procedure Triger_Crash_Natural is new Triger_Crash generic map (natural);
  begin
    if (rising_edge(Clk)) then
      Triger_Crash_Natural;
      if (Delay < Delay_Cycle) then Delay <= (Delay + 1);
      else Delay <= positive'low;
      end if;
    end if;
  end process;
end RTL;

context Work.Risc;
entity Test is
end Test;
architecture Bench of Test is begin MEM: entity Work.Memory port map ('0'); end Bench;

It's throw me:

# ** Note: (vsim-3812) Design is being optimized...

# ** Fatal: Unexpected signal: 11.

# ** Error: (vopt-2064) Compiler back-end code generation process terminated with code 232.

# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=2, Warnings=0.

# Error loading design

If I remove either the generic procedure or the delay incrementation, the bug disappear.

I hope these report help. Thanks you.

[RichardTanSY_Altera]

Let me check with the engineering team on the Test entity.  

On the other hand with the Memory entity, I not able to duplicate the error, could you help to guide me on how to get the error?

Best Regards,

Richard Tan

[RichardTanSY_Altera]

Are you using the Questa Intel FPGA Edition?

[RichardTanSY_Altera]

Do you able to provide the information based on my latest reply?

[RichardTanSY_Altera]

Just to follow up with you whether you have any update on this case?

[RichardTanSY_Altera]

Since there are no feedback for this thread, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.