Rom

[Altera_Forum]

hi everybody! 

i am working on the project of real time visual tracking. i have cyclone II board EP2C70. i have setup image processing pipeline. now i want to save small template (frame) in ROM, and i want to recal that frame for comparison on the video stream,during the process when video streaming will be flowing through the cyclone II board. can any boady know, how can i save a small template (frame) in the ROM?

[Altera_Forum]

If you want to code it in HDL search for ROM in here: http://www.altera.com/literature/hb/qts/qts_qii51007.pdf 

 I typically just use 'altsyncram' in ROM mode, you can use the megawizard GUI to have one generated for you.  Also in Quartus II if you have a verilog/VHDL file open you can click on "Edit" --> "Insert Template" and then navigate to the language you are using --> "Full Designs" --> "RAMs and ROMs" --> and select the kind of ROM you want and it'll drop it into your source file for you to hack up after.

[Altera_Forum]

sir i am using quartus v6.0 (available with the kit) 

"in the verilog HDL syntax" of insert template, there are three types of Full Design, which one i should use?  Full Design: Counter Full Design: Flipflop Full Design: Tri-state Buffer  these are three options in quartus v6.0

[Altera_Forum]

It appears that the version you are using doesn't have the templates I'm referring to. I'm pretty sure that 8.1 and later have those templates.

[Altera_Forum]

sir what should i do, while using v6.0? 

i think you are getting what i want to do by using ROM

[Altera_Forum]

See below the single port ROM templates 

-- Quartus II VHDL Template -- Single-Port ROM library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity single_port_rom is generic ( DATA_WIDTH : natural := 8; ADDR_WIDTH : natural := 8 ); port ( clk : in std_logic; addr : in natural range 0 to 2**ADDR_WIDTH - 1; q : out std_logic_vector((DATA_WIDTH -1) downto 0) ); end entity; architecture rtl of single_port_rom is -- Build a 2-D array type for the RoM subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0); type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t; function init_rom return memory_t is variable tmp : memory_t := (others => (others => '0')); begin for addr_pos in 0 to 2**ADDR_WIDTH - 1 loop -- Initialize each address with the address itself tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, DATA_WIDTH)); end loop; return tmp; end init_rom; -- Declare the ROM signal and specify a default value. Quartus II -- will create a memory initialization file (.mif) based on the -- default value. signal rom : memory_t := init_rom; begin process(clk) begin if(rising_edge(clk)) then q <= rom(addr); end if; end process; end rtl;  // Quartus II Verilog Template // Single Port ROM module single_port_rom # (parameter DATA_WIDTH=8, parameter ADDR_WIDTH=8) ( input addr, input clk, output reg q ); // Declare the ROM variable reg rom; // Initialize the ROM with $readmemb. Put the memory contents // in the file single_port_rom_init.txt. Without this file, // this design will not compile. // See Verilog LRM 1364-2001 Section 17.2.8 for details on the // format of this file. initial begin $readmemb("single_port_rom_init.txt", rom); end always @ (posedge clk) begin q <= rom; end endmodule

[Altera_Forum]

--- Quote Start ---  sir what should i do, while using v6.0?  --- Quote End ---  Is there any reason why you don't upgrade to a later version of Quartus? The latest web edition is a free download.

[Altera_Forum]

sir i am working on the BE project, to implement tracking algorithm in cyclone II.i have deadline for that project till the mid of January. this is the reason i am working on v6.0 

sir i have set video and image processing pipeline (AN:427) in quartus IIv6.0 in which real time video is flowing through the cyclone II board. now i am trying to upgrade that design by implementing tracking algorithm inside that.(i will implement tracking algorithm in dsp builder of v6.0 design) if i start work from 00 on v10.0 or v10.1 then i might not finish till that deadline.

[Altera_Forum]

I won't particularly suggest Quartus 10.x, rather a stable 9.0 or 9.1 version. But if you don't have problem with known V6.0 bugs affecting your design, I think it's O.K. to keep the version. It should be also noticed, that some Altera IP has been considerably changed through the years, depending on what you're using in the design, it may be a bad idea to change the version now.

[Altera_Forum]

thanks sir for your nice suggestion. 

sir i want to ask you one thing more. is there any possibility that i migrate my design from v6.0 to v10.0?  i have use in my design deinterlacer megacore, chroma resampler megacore, color space convertor megacore, scalar megacore. in v6.0 all thase megacore are in dsp builder but in v10.0 all these megacore are in quartus II.