Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Routing Resource Usage report per logic lock region.

ALMSlinger
새로운 기여자 I
1,341 조회수

Hello,

How do I report routing usage per logic lock region?  In the chip planner I can select the region and tool tip provides some information.  But I need a report for each region so that I can generate reports.

 

Thank you.
Best regards,

Sanjay

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sstrell
명예로운 기여자 III
1,338 조회수

This should be in the Compilation Report after a full compilation of the design.

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ALMSlinger
새로운 기여자 I
1,278 조회수

Thanks! But all I see is summary.  

ALMSlinger_0-1734046370558.png

 

Best regards,

Sanjay

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sstrell
명예로운 기여자 III
1,275 조회수

Check the Place Stage folder.

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ALMSlinger
새로운 기여자 I
1,260 조회수

Hmm... Do you mean this?  This doesn't report the route statistics and congestion.  

ALMSlinger_0-1734048047867.png

It would be nice if I could obtain report of what we can see by hovering over the logic logic lock region in chip planner.

ALMSlinger_1-1734050391099.png

 

Thank you.

Best regards,

Sanjay

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RichardTanSY_Altera
1,124 조회수

I'll check with the technical specialist to see if there's a way to check the routing utilization for the LL region.

Please expect slow response due to year end holiday.


Regards,

Richard Tan


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RichardTanSY_Altera
1,023 조회수

As of now, I have not receive any update from the engineering team. 

I will continue to follow up with the engineering team and provide you with an update as soon as possible.

Thank you for your patience and understanding. Please let me know if you have any questions or concerns.


Regards,

Richard Tan


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RichardTanSY_Altera
1,013 조회수

Unfortunately, we do not have the routing usage report for each Logic Lock region in the 'Compilation Report' .

As of now, you will need to hover in Chip Planner to check it.

I have filed a feature request and hopefully this feature will be added in the future Quartus release. Plan in 2nd half of 2025 (subject to change).


Since no further action is required from my side for this case, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.


Thank you and have a great day!


Best Regards,

Richard Tan


Regards,

Richard Tan



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RichardTanSY_Altera
524 조회수

Hi @ALMSlinger 

The tool specialist is looking into adding this feature now, but just wanted to clarify a few things:

The only LLR-specific statistics that are currently reported are the "Logic Lock Region Usage Summary", regarding placed elements.

The most likely reason why the reports were done this way is that, while an element such as an ALM will fully sit inside an LLR, a wire can potentially pass through multiple LLRs depending on the length of the wire and the size of the LLR. In this case it becomes a bit difficult to report a useful representation of the routing utilization in any given LLR.

If you could clarify what exactly you were looking for from your requested report, and how you intend to utilize the report, perhaps it could provide some insight into what we need to add for this feature.

Regards,
Richard 

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