Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

SImulation error

Kurtlin
Beginner
252 Views

 

SW in use:

Quartus Prime 20.1.1

University Program VWF 

 

AHDL file:

-- OUTPUT declarations

Dataout[][] = OUTPUT_LATCH_ff[][].q;


Data_OUT1[] = OUTPUT_LATCH_ff[0][].q;
Data_OUT2[] = OUTPUT_LATCH_ff[1][].q;
Data_OUT3[] = OUTPUT_LATCH_ff[2][].q;
Data_OUT4[] = OUTPUT_LATCH_ff[3][].q;

 

when the project is simulated the 

Data_OUTX[] shows the correct waveform

Dataout[][] shows XX

 

any idea why the 2 dimensional bus is not simulating correctly??

 

best regards

Kurt

 

 

 

 

0 Kudos
2 Replies
SyafieqS
Moderator
226 Views

Kurt,


More information needed here. A snapshot of the error message and the simulation if possible?


SyafieqS
Moderator
147 Views

Kurt,


May I know if there is any update regarding my previous request?



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