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SOPC Builder Component Editor in Quartus II 10.1

Altera_Forum
Honored Contributor II
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Hi all! 

 

In Quartus II 10.1, there are changes in the SOPC Builder component editor: 

 

Now there are separate interfaces for clock signals and associated reset signals, and we specify an associated clock interface to each reset interface. Why not. 

 

Also, in reset interfaces, there is a parameter called "synchronousEdges", that can be set to either "NONE", "BOTH", or "DEASSERT". what is the purpose of that? 

 

Thanks 

 

- Julien
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Altera_Forum
Honored Contributor II
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This field describes what type of reset synchronization the component requires. 

 

None = component does it's own internal reset synchronization so the tools won't bother doing this for you 

 

Deassert = component requires that the incoming reset be asserted asynchronously and deasserted synchronously. 

 

Both = component requires that the reset be asserted and deasserted synchronously. 

 

So historically SOPC Builder always assumed "Deassert" where all the resets would get bundled together, synchronized per clock domain, and each synchronized reset sent throughout the system on a per clock domain basis. Components were always asynchronously reset and were brought out of reset synchronously (Deassert).
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Altera_Forum
Honored Contributor II
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Thanks a lot!

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