SOPC to QSYS migration, Increasing number of Logic Cells used

[Altera_Forum]

Hi all,  

 I'm trying to migrate an SOPC design to QSYS (using the "direct method" by opening the .sopc file from the QSYS environment), and I'm now bumping into a resource usage problem.   I'm using the Cyclone III (EP3C55) having around 55,000 logic elements.   Before the migration from SOPC to QSYS, the design was using:   Total logic elements 49,475 / 55,856 ( 89 % ) Total memory bits 1,559,190 / 2,396,160 ( 65 % )   After the migration, the resource usage changed:   Total logic elements: 55,576 / 55,856 ( 99 % ). Total memory bits 954,342 / 2,396,160 ( 40 % )     From this, I can no longer get the video chain in my design to function properly (nothing is displayed on the output screen). Also, the TSE_MAC module is not working as it did previously. (I haven't testet the rest of the design/IP's, but there might be similar issues).   I'm guessing Quartus II is having trouble meeting timing when placing and routing the design, due to congestion is the FPGA (nearly all the LE's are used).   Also, I tried "manually" building a new QSYS design using the same IP's as in the SOPC version. Doing so, I was able to almost get the entire design running, except, when I add the second video processing chain (the design is complete after adding the second video processing chain) to the QSYS design, the resource usage hits:   Total logic elements 53,548 / 55,856 ( 96 % ) Total memory bits 1,179,461 / 2,396,160 ( 49 % )   and things stop working as they should.   From this, how can the migration take place without hitting the upper limits of the resource usage (LE's) ?      Saber890

[Altera_Forum]

change the pipeline setting in qsys to 0. This will more closely mimic sopc builder. Also, look at the resets, the conversion can make mistakes with resets. 

 You will most likely have to look at your sdc constraints again as well.

[Altera_Forum]

Are you saying that the pipelines should be removed from the QSYS design all togheter? Without buffering the read/write accesses it might be difficult to make the design work. 

 In my design there are several Masters and a slave (NiosII, Deinterlacer, Framebuffer, Framereader) connected an external memory controller (DDR2 SDRAM with ALTMEMPHY). The Deinterlacer uses 5 write/read Masters, and inorder to get the design to work, I placed a pipeline stage between the Deinterlacer and the external memory controller. I'm not sure I can make the design work by removing the pipeline stage.   For the SOPC to QSYS migration, where I recreated the design in QSYS, I'm only using a single reset signal for the entire design, so there are no "accidental" reset signals waiting to happen.   I'll try looking into the SDC constraints again, to see where the timing is failing.   Regards,   Saber890

[Altera_Forum]

no, if you have pipeline stages manually placed in the design then i am not suggesting you remove them. What i am suggesting is that if you want to generate rtl on par with what was generated in sopc builder, you need to (under the project settings tab i believe), change the default of 1 pipeline stage settings to 0 to match sopc builder behaviour. 

 --dalon