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Beginner
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SPI (3-Wire Serial) Intel FPGA IP sending 16 bits for every byte write

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Hello,

I'm having an issue with the SPI port sending out 16 clock cycles every time I try and write a single byte using a NIOS2f.

I've verified that the Data Register Width is set to 8 in Platform Designer.

If I call the following:

alt_u8 tx_buf[4] = {0};
alt_u8 rx_buf[4] = {0};

tx_buf[0] = 0x10;
tx_buf[1] = 0x20;
tx_buf[2] = 0x40;
tx_buf[3] = 0x80;

alt_avalon_spi_command(ADC_SPI_BASE, 0, 4, &tx_buf[0], 4, &rx_buf[0], 0);

I see the attached on my logic anaylzer.

Also attaching screenshot of the SPI configuration in Platform Designer.

Lastly, when I generate the system.h file for use with the NIOS, I see this:

/*
* adc_spi configuration
*
*/

#define ADC_SPI_BASE 0x101300
#define ADC_SPI_CLOCKMULT 1
#define ADC_SPI_CLOCKPHASE 0
#define ADC_SPI_CLOCKPOLARITY 0
#define ADC_SPI_CLOCKUNITS "Hz"
#define ADC_SPI_DATABITS 8
#define ADC_SPI_DATAWIDTH 16
#define ADC_SPI_DELAYMULT "1.0E-9"
#define ADC_SPI_DELAYUNITS "ns"
#define ADC_SPI_EXTRADELAY 0
#define ADC_SPI_INSERT_SYNC 0
#define ADC_SPI_IRQ 2
#define ADC_SPI_IRQ_INTERRUPT_CONTROLLER_ID 0
#define ADC_SPI_ISMASTER 1
#define ADC_SPI_LSBFIRST 1
#define ADC_SPI_NAME "/dev/adc_spi"
#define ADC_SPI_NUMSLAVES 1
#define ADC_SPI_PREFIX "spi_"
#define ADC_SPI_SPAN 32
#define ADC_SPI_SYNC_REG_DEPTH 2
#define ADC_SPI_TARGETCLOCK 128000u
#define ADC_SPI_TARGETSSDELAY "0.0"
#define ADC_SPI_TYPE "altera_avalon_spi"
#define ALT_MODULE_CLASS_adc_spi altera_avalon_spi

 

Is the fact that data_width 16 part of my issue?  If so, how do I change it?

 

Thank you for any and all suggestions.

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Moderator
58 Views

Hi Tyler,

 

Glad you had solved the issue. Most of the time, it is always recommended to regenerate you IPs. The feature you said if you turn it on, it will automatically generates IP before compiling the design as it indirectly  terminates the manual way where you generate in PD --> add new .qip --> and recompile.

 

Thanks,

Regards

 

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2 Replies
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Beginner
74 Views

I was able to figure out this problem.

It was because Quartus was not regenerating the design files for the IP cores when compiling.  So even though my NIOS thought it was writing 8 bits to the SPI IP, the SPI registers were still 16 bits wide.

To fix it, I opened the project in quartus, went to tools > options > IP settings and checked the radio button next to Always regenerate design files for IP cores.

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Highlighted
Moderator
59 Views

Hi Tyler,

 

Glad you had solved the issue. Most of the time, it is always recommended to regenerate you IPs. The feature you said if you turn it on, it will automatically generates IP before compiling the design as it indirectly  terminates the manual way where you generate in PD --> add new .qip --> and recompile.

 

Thanks,

Regards

 

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