SUm of table

Altera_Forum · ‎02-22-2014

Hi,

Please can you help me to write a Verilog code to calculate sum of table, I have a code that’s calculate with this manner.

generate

if(z == 1)

assign x = y[0];

else if (z == 2)

assign x = y[0] + y[1];

else if (z == 3)

assign x = y[0] +y[1] + y[2] ;

endgenerate

I need to let’s this code a generic using a boucle for to calculate sum of table using always block.

Thank you for your helps.

Altera_Forum · ‎02-24-2014

You don't say how wide your different signals are...

Assuming z is 2-bits wide, y 3-bits and x 1-bit:

reg x;
always @ (*)
case (z):
  1 : x = y;
  2 : x = y + y;
  3 : x = y + y + y;
endcase

This would also work if x & y are wider - but the same width as each other - and y an array.

You'll need to specify what happens to x in the case of z == 0.

Regards,

Alex

Altera_Forum · ‎02-25-2014

Thank you very much. problem resolved with this solution.