Sequential output of FSM in Verilog

[Altera_Forum]

Hi, 

 I did a little experiment in Verilog as I set up a simple FSM and generate sequential output using the following code:  always@(posedge clk) begin case(state) st5:begin TestSignal <= 1; end default: TestSignal <= 0; endcase end  If I remember correctly, in VHDL similar code (clocked PROCESS I guess) would raise 'TestSignal' one clock cycle after entering 'state=st5'; however in Verilog 'TestSignal' rises as soon as the state transits to 'st5'. If this is way it works, then what's the difference between using always@(posedge clk) and always@(state) for the above code? Any hint?  Thanks a lot.

[Altera_Forum]

always@(posededge clk) is the equvalent of a clocked process with if rising_edge(clk) in VHDL. 

 It's not exactly correct to say it "would raise 'TestSignal' one clock cycle after entering 'state=st5'". This is only true if state is set with the same clock edge. Generally, state can be set at any time between the previous and the present clock edge.

[Altera_Forum]

--- Quote Start ---  always@(posededge clk) is the equvalent of a clocked process with if rising_edge(clk) in VHDL.  It's not exactly correct to say it "would raise 'TestSignal' one clock cycle after entering 'state=st5'". This is only true if state is set with the same clock edge. Generally, state can be set at any time between the previous and the present clock edge.  --- Quote End ---    Thanks FvM,  I understand that always@(posedge clk) is equivalent to clocked process with rising_edge(clk) in VHDL, that's why I think a registered output of FSM can be described directly by using  always@(posedge clk) (namely 'TestSignal' is supposed to rise in the following clock cycle if the state transits to st5 in the current clock cycle, not necessarily at clock edge), however in my experiment the output came out within the same clock cycle as the one where the state transits to st5. This is what confuses me.  I'v no idea what goes wrong, now in order to have a registered output, I need to raise a flag (combinatorial signal) when the state transit to st5, then use always@(posedge clk) block to trigger the output TestSignal when the flag rises. Why can't I use always@(posedge clk) block to monitor the state directly?  Thanks

[Altera_Forum]

--- Quote Start ---  Thanks FvM,  I understand that always@(posedge clk) is equivalent to clocked process with rising_edge(clk) in VHDL, that's why I think a registered output of FSM can be described directly by using  always@(posedge clk) (namely 'TestSignal' is supposed to rise in the following clock cycle if the state transits to st5 in the current clock cycle, not necessarily at clock edge), however in my experiment the output came out within the same clock cycle as the one where the state transits to st5. This is what confuses me.  I'v no idea what goes wrong, now in order to have a registered output, I need to raise a flag (combinatorial signal) when the state transit to st5, then use always@(posedge clk) block to trigger the output TestSignal when the flag rises. Why can't I use always@(posedge clk) block to monitor the state directly?  Thanks  --- Quote End ---    If your st5 indeed transitions at current clock edge then it is sampled on next clock edge to be known and so raise TestSignal.  If you are getting both at same edge then you are doing something wrong. For example your state transitions on a different clock. You better show more of your code.